1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. Golden System Reference Design and Design Examples 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Intel® Stratix® 10 SoC FPGA Boot Flow 8. Intel® Stratix® 10 SoC FPGA Boot User Guide Archives 9. Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide
4.6.3. HPS Boot First
In this case, the device reads a small phase 1 bitstream from QSPI flash and uses it to configure the HPS IO, HPS DDR, and bring up the HPS software. Then later the HPS software can configure the FPGA fabric using the typically much larger phase 2 configuration bitstream. The following figure shows an overview of the process:
Figure 17. Configuration from QSPI using HPS Boot First
The following steps are involved:
- Compile hardware project with Intel® Quartus® Prime to obtain the SOF file.
- Compile the HPS FSBL source code to obtain the HPS FSBL hex file, or use a precompiled one.
- Use Programming File Generator to create the following files:
- HPS JTAG Indirect Configuration (JIC) file: contains the small phase 1 configuration bitstream and a small SDM helper firmware image used by the Intel® Quartus® Prime Programmer to write the bitstream to flash.
- [Optional] HPS Raw Programming Data (RPD) File: contains the small phase 1 configuration bitstream in simple binary format. Can be written to flash with a 3rd party programmer, such as U-Boot.
- Core RBF file: contains the phase 2 configuration bitstream, to be used by HPS software to configure the FPGA fabric.
- [Optional] Map file: describes the flash placement and usage in human-readable text format.
- Use the Intel® Quartus® Prime Programmer to write the JIC image to QSPI flash. Alternatively use a 3rd party programmer to write the RPD image to flash.
- Set MSEL to QSPI, then power up, power cycle or toggle nCONFIG to cause the device to configure itself from QSPI.
- HPS software starts running, beginning with HPS FSBL.
- Later HPS software configures the FPGA fabric by using the phase 2 Core RBF bitstream.
Note: The phase 1 and phase 2 configuration bitstreams must be created by the exact same Intel® Quartus® Prime Programming File Generator version, including the same firmware patches. Also, the phase 1 and phase 2 configuration bitstreams must have the same HPS IO settings, including the HPS DDR settings. If these conditions are not both met, the phase 2 configuration fails.
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