1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. Golden System Reference Design and Design Examples 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Intel® Stratix® 10 SoC FPGA Boot Flow 8. Intel® Stratix® 10 SoC FPGA Boot User Guide Archives 9. Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide
4.8. Configuration via Protocol
In the Configuration via Protocol (CvP) case, a small QSPI flash image is configured first, which brings up the PCIe* interface quickly. Then, later, the PCIe* host computer configures the fabric with the Core RBF file.
Figure 27. Configuration over Protocol
The following steps are involved:
- Compile hardware project with Intel® Quartus® Prime to obtain the SOF file.
- Compile the HPS FSBL source code to obtain the HPS FSBL hex file, or use a precompiled file.
- Use Programming File Generator to create the following files:
- Peripheral JIC File: contains the initial configuration bitstream (including peripheral configuration data and SDM firmware) and a small SDM helper firmware image used by the Intel® Quartus® Prime Programmer to write the bitstream to flash.
- [Optional] Peripheral RPD File: contains the same initial configuration bitstream as the Peripheral JIC file, in simple binary format. Can be written to flash with a 3rd party programmer, such as U-Boot.
- Core RBF File: contains the FPGA configuration data, to be used by PCIe host software later to configure the fabric. The HPS FSBL is included in the Core RBF file.
- [Optional] Map File: describes the actual flash usage in human-readable text format.
- The FPGA device is configured from the initial peripheral bitstream from QSPI flash, which brings up the PCIe interface.
- The PCIe host later configures the core fabric over PCIe. This includes downloading and running HPS FSBL.
Note: When using CvP, only the FPGA configuration first mode is supported.
Did you find the information on this page useful?