Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 7/26/2022
Public

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2.1.2. Secure Device Manager

Once the Intel Stratix 10 SoC FPGA exits POR, the SDM samples the MSEL[2:0] pins1 to determine the boot source. Next, the device configures the SDM I/Os according to the selected boot source interface and the SDM retrieves the configuration bitstream through the interface. SDM can boot from the following boot sources listed in the following table.
Table 3.  Available SDM Boot Sources for the Intel Stratix 10 SoC FPGA
SDM Boot Source Details
Avalon-ST (x8/x16/x32) Supported
JTAG Supported
Active Serial (AS)/ Quad SPI Supported. SDM only boots in x4 mode for active serial flash and Micron* MT25Q flash. Other supported quad SPI flash devices boot in x1 mode. After the configuration firmware loads into the SDM, the SDM can switch the flash into x4 mode.
The typical configuration bitstream for FPGA configuration first contains:
  1. Configuration firmware for the SDM
  2. FPGA I/O and HPS external memory interface (EMIF) I/O configuration data
  3. FPGA core configuration data
  4. HPS FSBL code and FSBL hardware handoff binary data

The SDM completes the configuration of the FPGA core and I/O, and then copies the HPS FSBL code and HPS FSBL hardware handoff binary to the HPS on-chip RAM.

1 The MSEL[2:0] pins are multiplexed with the SDM_IO[9], SDM_IO[7], SDM_IO[5] pins respectively.

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