Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 7/26/2022
Public

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3.1.3. First-Stage Bootloader

After the SDM releases the HPS from reset, the FSBL initializes the HPS. Initialization includes configuring clocks, HPS dedicated I/Os, and peripherals.
Note: In HPS first boot mode, the SDM, HPS OSC and HPS EMIF clocks must be running stable and set at the correct frequency before you begin any part of the configuration sequence.

In HPS first boot mode, phase 1 configuration is successful as long as HPS OSC and HPS EMIF clocks are running stable.

For a generic transceiver use case, if the XCVR ref clock is not running during phase 2 configuration, the phase 2 configuration still succeeds.

For a PCIe use case, if the PCIe ref clock is not running during phase 2 configuration, the configuration fails.

You can create the FSBL from one of the following sources:

  • U-Boot secondary program loader (SPL)
    • Intel® provides the source code for U-Boot on GitHub.
  • Arm* Trusted Firmware
    • Intel provides the source code for the Arm* Trusted Firmware on GitHub.

The latest source code is also available on the Intel public git repository.

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