Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 7/26/2022
Public

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Document Table of Contents

9. Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide

Document Version Intel® Quartus® Prime Version Changes
2022.07.26 21.4 Made the following changes:
  • Added description of the REBOOT_HPS in the Reset section.
  • Added information about the maximum size of the .core.rbf and bit-stream in the Programming File Generator section.
  • Added the Intel® Stratix® 10 SoC FPGA Boot User Guide Archives section
  • Made changes to Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide
    • Added the Intel® Quartus® Prime Version column
    • Converted this section from an appendix to a chapter
2021.11.10 21.1 Replaced the Supported QSPI Devices table with a link to the Intel® Supported Configuration Devices web page.
2021.05.28 21.1
  • Replaced the Creating a Configuration Bitstream for Intel® Stratix® 10 SoC FPGA section with the new Creating the Configuration Files section
  • Replaced the Generating the Linux Kernel Image section with the new Golden System Reference Design and Design Examples section
  • Renamed section Configuring the FPGA from SSBL and OS section to Configuring the FPGA Fabric from HPS Software
  • Renamed section Configuring the FPGA Using the U-Boot SSBL section to Configuring the FPGA Fabric from U-Boot
  • Renamed section Configuring the FPGA Using the Linux Operating System section to Configuring the FPGA Fabric from Linux
  • Replaced the tool: Arm* Development Studio 5* Intel® SoC FPGA Edition with Arm* Development Studio* Intel® SoC FPGA Edition
  • Removed the following sections from Debugging the HPS Boot Loader Using the Arm* Development Studio* Intel® SoC FPGA Edition :
    • Selecting the HPS Debug Interface
    • Configuring the FPGA and run the Debug FSBL
    • Creating the Debug Configuration
    • Debugging the First Stage Boot Loader (FSBL)
    • Debugging U-Boot
2020.12.04 20.2 Added a restriction to the Boot Flow Overview section that the phase 1 and phase 2 configuration files must be generated from the same Intel® Quartus® Prime Pro Edition software version.
2020.09.15 19.2
  • Added information about the differences between H- and L-tile regarding clock requirements prior to configuration in Boot Flow Overview.
  • Added information clock requirements for HPS first boot mode; and what is required for phase 1 and phase 2 in First-Stage Bootloader.
2020.06.30 19.2 Removed support for the SD/MMC configuration scheme in Intel Stratix 10 devices.
2019.12.19 19.2 Made the following changes:
  • Removed all references to EPCQ-L. This flash device is obsolete.
  • Replaced EPCQL1024 with MT25QU02G in quartus_pfg commands.
  • Removed all references to prebuilt binaries or sources inside the SoC EDS. These files are no longer included in the distribution.
  • Corrected directory path in Compiling the SRAM Object File. It should include 19.3.
  • Revised Compiling U-Boot FSBL and SSBL to get the source code from the GitHub repository.
  • Updated the version of socfpga in Compiling the Linux Kernel Image
  • Revised the debugging section.
2019.12.16 19.2 Made the following changes:
  • Changed all commands to convert programming files to use the quartus_pfg instead of quartus_cpf. The quartus_cpf command does not handle some of the advanced security features that Intel® Stratix® 10 devices support.
  • Added the following note to the Single SDM Flash topic: Due to a problem in the Intel® Quartus® Prime Pro Edition Software, if you specify the HPS boot from FPGA parameter on the FPGA Interfaces tab of the Intel® Arria® 10 Hard Processor System Intel® Arria® 10 FPGA IP GUI, this information has no effect on HPS behavior.
  • Removed statement in Creating the Raw Programming Data ( *.rpd ) File For Flash Programming topic saying that the .rpd file generated is the same size as the configuration device. This statement is not true for Intel® Stratix® 10 and later device families.
2019.07.25 19.2

Note added to explain HPS First "Phase 1 configuration" and "Phase 2 configuration" terminology in Boot Flow Overview .

2018.09.24 18.0
  • Added references to the Single QSPI Flash Boot Example.
  • Updated the filenames in accordance to the SoC EDS 18.1 version.
  • Added reference to the Micron MT25Q Support knowledge base.
  • Added the information about Testing FPGA Reconfiguration at Kernel Level.
2018.05.01 18.0 Initial release.

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