Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 7/26/2022
Public

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Document Table of Contents

4.2.1. Device and Pin Options

The device and pin options can be accessed from Intel® Quartus® Prime, by going to Assignments > Device > Device and Pin Options. The most important options related to configuration and HPS boot are:
  • General > Configuration Clock Source : allows using an internal oscillator or an external input clock for configuration purposes.
  • Configuration > Configuration Scheme: allows selecting the configuration source:
    • Active Serial x4
    • AVST x8
    • AVST x16
    • AVST x32
  • Configuration > Active Serial Clock Source: allows selecting the QSPI clock speed when Active Serial x4 mode is selected
  • Configuration > Configuration Pin Options: allows selecting SDM pin behavior for configuration purposes
  • Configuration > HPS/FPGA Configuration Order: allows selecting FPGA Configuration First (called After INIT_DONE) or HPS Boot First (called HPS First) modes.
  • Configuration > HPS Debug Access Port (DAP): allows the HPS JTAG port to be connected to HPS Pins, FPGA Pins or Disabled. It is typically connected to SDM pins, so you can have a single JTAG connection covering both SDM and HPS.
  • CvP Settings > Configuration via Protocol: can be selected as Initialization and update or Off.

For more information about these options, refer to the Intel® Stratix® 10 Configuration User Guide.

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