Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 7/26/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.2.1. External Configuration Host Only

Figure 7. External Configuration Host Only

In this example, the external configuration host ( Avalon® Streaming or JTAG) provides the SDM a configuration bitstream that consists of the following components:

  • SDM configuration firmware
  • HPS EMIF I/O configuration data
  • HPS FSBL code and HPS FSBL hardware handoff binary

However, because the HPS SSBL or subsequent OS files are not part of the bitstream, the HPS can only boot up to the FSBL stage. This setup is applicable if you are using the FSBL to run simple applications such as Bare Metal applications.

Because the FPGA core is not configured, the FSBL must retrieve the SSBL from external sources, such as the HPS EMAC interface. The U-Boot FSBL source code that Intel® provides does not include source code to support SSBL retrieval through the HPS EMAC interface. You must implement the Ethernet software stack in the FSBL separately. Similarly, after the SSBL loads, the SSBL must retrieve the FPGA core and I/O configuration file from an external source as well.

Table 7.  Supported Configuration Boot and SSBL Sources
SDM Configuration Host SSBL Source Details
Avalon® streaming HPS Ethernet Not supported in U-Boot FSBL code that Intel provides.