Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 7/26/2022
Public

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4.7.1.2. Creating Configuration Files Using Graphical Interface

The following example creates the AVST configuration files for FPGA first mode using the Programming File Generator in GUI mode:

  1. Start the Programming File Generator in GUI mode by running the qpfgw command.
  2. Select the Device Family to be Intel® Stratix® 10.
  3. Select the Configuration mode to be AVST x8, AVST x16 or AVST x32.
  4. In the Output Files tab:
    1. Change the output file Name to “design”.
    2. Check Raw Binary File (.rbf) option – the others are grayed out.
    The Intel® Quartus® Prime Programming File Generator window is displayed:
    Figure 22.  Intel® Quartus® Prime Programming File Generator Pro Edition Window: Output Files
  5. Switch to Input Files tab by clicking it. In the Input Files tab, do the following:
    1. Click the Add Bitstream button, browse to your SOF file, then click Open.
    2. Click the newly added design.sof file, then click Properties. In the HPS settings > Bootloader section, click the “..” browse button, go to the location of your HPS FSBL hex file, select it and click Open.
    The Intel® Quartus® Prime Programming File Generator window is displayed:
    Figure 23.  Intel® Quartus® Prime Programming File Generator Pro Edition Window: Input Files
  6. Click the Generate button. Once the files are generated, a confirmation message is received.
  7. Optionally, go to File > Save or File > Save As to save the configuration in a .pfg file. You can generate the output again by applying the same options by running the command line version of the tool like this: quartus_pfg -c <filename.pfg>.

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