Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 7/26/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.7.1. FPGA Configuration First

The following figure shows an overview of the process:
Figure 21. Configuration over Avalon Streaming Using FPGA Configuration First

The following steps are involved:

  1. Compile hardware project with Intel® Quartus® Prime to obtain the SOF file.
  2. Compile the HPS FSBL source code to obtain the HPS FSBL hex file, or use a precompiled file.
  3. Use Programming File Generator to create the following files:
    Raw Binary File (RBF): contains the configuration bitstream in binary format.
  4. Set MSEL to the AVST mode.
  5. Power up, power cycle or toggle nCONFIG on the device.
  6. Use an external master connected over AVST to configure the device using the RBF File.