1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. Golden System Reference Design and Design Examples 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Intel® Stratix® 10 SoC FPGA Boot Flow 8. Intel® Stratix® 10 SoC FPGA Boot User Guide Archives 9. Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide
4.5. Configuration over JTAG
In this case, the configuration bitstream is sent to the device over JTAG with the help of the Intel® Quartus® Prime Programmer. The following figure shows an overview of the process:
Figure 12. Configuration over JTAG
The following steps are involved:
- Compile hardware project with Intel® Quartus® Prime to obtain the SOF file.
- Compile the HPS FSBL source code to obtain the HPS FSBL hex file or use a precompiled HPS FSBL hex file.
- Add the HPS FSBL hex file to the SOF file to obtain the HPS SOF File. SOF files resulted from compiling hardware designs which have HPS instantiated cannot be used directly to configure the device.
- Use the Intel® Quartus® Prime Programmer to configure the device over JTAG with the resulted HPS SOF file. The required firmware to run on the SDM must be downloaded on the device by the Intel® Quartus® Prime Programmer.
Note: Only FPGA configuration first mode is supported when configuring over JTAG.
Run the following command to add the HPS FSBL hex file to the SOF file to create the HPS SOF file:
quartus_pfg -c design.sof design_hps.sof -o hps_path=fsbl.hex
The input and output files for this command are:
- Input Files:
- Output File:
Note: Generating the HPS SOF file is supported only from the command line.
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