Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 7/26/2022
Public

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2.2.1. External Configuration Host Only

Figure 2. External Configuration Host Only

In this example, the external configuration host ( Avalon® streaming or JTAG) provides the SDM with a configuration bitstream that consist of:

  • SDM configuration firmware
  • FPGA I/O and HPS EMIF I/O configuration data
  • FPGA core configuration data
  • HPS FSBL code and HPS FSBL hardware handoff binary

Because the HPS SSBL (or subsequent OS) is not part of the bitstream, the HPS can only boot up to the FSBL stage. This setup is applicable if you are using the FSBL to run simple applications (for example, Bare Metal applications).

You can use the FSBL to retrieve the SSBL from other sources, such as through the HPS Ethernet MAC interface. To implement these modes of access, you must create a working Ethernet software stack in the FSBL.

Table 4.  Supported Configuration Boot and SSBL Source
SDM Configuration Host SSBL Source Details
Avalon® streaming HPS Ethernet Not supported in U-Boot FSBL code provided by Intel.
JTAG

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