Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 7/26/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.7.2. HPS Boot First

In this case, the device gets first configured with a small phase 1 bitstream from QSPI flash, the HPS IO, HPS DDR are configured and HPS starts running the FSBL. Then at a later time the HPS software can configure the FPGA fabric using the typically much larger phase 2 configuration bitstream. The following figure shows an overview of the process:
Figure 24. Configuration over Avalon Streaming Using HPS Boot First
  1. Compile hardware project with Intel® Quartus® Prime to obtain the SOF file.
  2. Compile the HPS FSBL source code to obtain the HPS FSBL hex file, or use a precompiled one.
  3. Use Programming File Generator to create the following files:
    • Raw Binary File (RBF): contains the small phase 1 configuration bitstream.
    • Core RBF File: contains the typically much larger phase 2 configuration bitstream, to be used by HPS software later to configure the fabric.
    1. At a later time HPS software configures the FPGA fabric by using the phase 2 Core RBF bitstream.
  4. Set MSEL to the AVST mode.
  5. Power up, power cycle or toggle nCONFIG on the device.
  6. Use an external master connected over AVST to configure the device using the phase 1 bitstream.

    HPS software starts running, beginning with HPS FSBL.

    At a later time HPS software configures the FPGA fabric by using the phase 2 Core RBF bitstream.

Did you find the information on this page useful?

Characters remaining:

Feedback Message