4.7.2. HPS Boot First
- Compile hardware project with Intel® Quartus® Prime to obtain the SOF file.
- Compile the HPS FSBL source code to obtain the HPS FSBL hex file, or use a precompiled one.
- Use Programming File Generator to create the following files:
- Raw Binary File (RBF): contains the small phase 1 configuration bitstream.
- Core RBF File: contains the typically much larger phase 2 configuration bitstream, to be used by HPS software later to configure the fabric.
- At a later time HPS software configures the FPGA fabric by using the phase 2 Core RBF bitstream.
- Set MSEL to the AVST mode.
- Power up, power cycle or toggle nCONFIG on the device.
- Use an external master connected over AVST to configure the device using the phase 1 bitstream.
HPS software starts running, beginning with HPS FSBL.
At a later time HPS software configures the FPGA fabric by using the phase 2 Core RBF bitstream.
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