Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 7/26/2022
Public

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Document Table of Contents

1.1. Glossary

Table 1.   Intel® Stratix® 10 SoC FPGA Boot Glossary
Term Definition
EMIF External memory interface
*.pof Programming object file; contains data to configure the FPGA portion of the SoC and additionally, may contain the HPS first-stage payload. This file is typically stored in external flash such as quad serial peripheral interface (Quad SPI) or common flash interface (CFI) flash.
FW Firmware; Controls and monitors software stored in Secure Device Manager's (SDM) read-only memory.
HPS Hard Processor System; the SoC portion of the device, consisting of a quad core Arm* Cortex-A53 processor, hard IPs, and HPS I/Os in the Intel® Stratix® 10 SoC FPGA.
HPS EMIF I/O section Part of the raw binary file (*.rbf) that configures the EMIF I/O used by the HPS
FPGA I/O section Part of the *.rbf that configures the I/O assigned to the FPGA core
Core *.rbf Core raw binary file; FPGA core image file that includes logic array blocks (LABs), digital signal processing (DSP), and embedded memory. The core image consists of a single reconfigurable region, or both static and reconfigurable regions.
FSBL First-stage Bootloader for HPS
*.jic JTAG Indirect Configuration file that allows programming through JTAG
OS Operating system
*.rbf Raw binary file representing the FPGA bitstream
*.rpd Raw Programming Data file for AS devices
*.sof SRAM object file which contains the bitstream for the primary FPGA design. Firmware is not part of the *.sof.
SSBL Second-stage Bootloader for HPS
SDM Secure Device Manager; a triple-redundant processor-based block that manages FPGA configuration and hard processor system (HPS) secure boot process in Intel® Stratix® 10 devices.

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