Cyclone V Device Datasheet

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ID 683801
Date 5/23/2023
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Document Table of Contents
Document Table of Contents x
Cyclone V Device Datasheet
Cyclone V Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for Cyclone® V Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications OCT Variation after Power-Up Calibration Pin Capacitance Hot Socketing Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Differential HSTL and HSUL I/O Standards Differential I/O Standard Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance HPS Specifications
Transceiver Performance Specifications x
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain Typical TX VOD Setting for Cyclone® V Transceiver Channels with termination of 100 Ω Transmitter Pre-Emphasis Levels Transceiver Compliance Specification
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Performance Specifications Memory Block Performance Specifications
Periphery Performance x
High-Speed I/O Specifications DLL Frequency Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications Duty Cycle Distortion (DCD) Specifications
HPS Specifications x
HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Arm* Trace Timing Characteristics UART Interface GPIO Interface CAN Interface HPS JTAG Timing Specifications
HPS PLL Specifications x
HPS PLL VCO Frequency Range HPS PLL Input Clock Range HPS PLL Input Jitter
Configuration Specifications x
POR Specifications FPGA JTAG Configuration Timing FPP Configuration Timing Active Serial (AS) Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme Passive Serial (PS) Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Oscillator Frequency Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
I/O Timing x
Programmable IOE Delay Programmable Output Buffer Delay
Cyclone V Device Datasheet

Transceiver Compliance Specification

The following table lists the physical medium attachment (PMA) specification compliance of all supported protocol for Cyclone® V GX, GT, SX, and ST devices. For more information about the protocol parameter details and compliance specifications, contact your Intel Sales Representative.

Table 29.  Transceiver Compliance Specification for All Supported Protocol for Cyclone® V GX, GT, SX, and ST Devices
Protocol Sub-protocol Data Rate (Mbps)
PCIe* PCIe* Gen1 2,500
PCIe* Gen250 5,000
PCIe* Cable 2,500
XAUI XAUI 2135 3,125
Serial RapidIO® (SRIO) SRIO 1250 SR 1,250
SRIO 1250 LR 1,250
SRIO 2500 SR 2,500
SRIO 2500 LR 2,500
SRIO 3125 SR 3,125
SRIO 3125 LR 3,125
SRIO 5000 SR 5,000
SRIO 5000 MR 5,000
SRIO 5000 LR 5,000
Common Public Radio Interface (CPRI) CPRI E6LV 614.4
CPRI E6HV 614.4
CPRI E6LVII 614.4
CPRI E12LV 1,228.8
CPRI E12HV 1,228.8
CPRI E12LVII 1,228.8
CPRI E24LV 2,457.6
CPRI E24LVII 2,457.6
CPRI E30LV 3,072
CPRI E30LVII 3,072
CPRI E48LVII 51 4,915.2
CPRI E60LVII51 6,144
Gbps Ethernet (GbE) GbE 1250 1,250
OBSAI OBSAI 768 768
OBSAI 1536 1,536
OBSAI 3072 3,072
Serial digital interface (SDI) SDI 270 SD 270
SDI 1485 HD 1,485
SDI 2970 3G 2,970
VbyOne VbyOne 3750 3,750
HiGig+ HIGIG 3750 3,750
Related Information
50 For PCIe* Gen2 sub-protocol, Intel recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone® V GT and ST FPGA systems which ensure full compliance to the PCIe* Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended in Cyclone® V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone® V Devices chapter.
51 For CPRI E48LVII and E60LVII, Intel recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter specification at 4.9152 Gbps ( Cyclone® V GT and ST devices) and 6.144 Gbps ( Cyclone® V GT and ST devices only). For more information about the maximum full duplex channels recommended in Cyclone® V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone® V Devices chapter.
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