Cyclone V Device Datasheet

ID 683801
Date 5/23/2023
Document Table of Contents

Quad SPI Flash Timing Characteristics

Table 43.  Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Cyclone® V Devices
Symbol Description Min Typ Max Unit
Fclk SCLK_OUT clock frequency (External clock) 108 MHz
Tqspi_clk QSPI_CLK clock period (Internal reference clock) 2.32 ns
Tdutycycle SCLK_OUT duty cycle 45 55 %
Tdssfrst Output delay QSPI_SS valid before first clock edge 1/2 cycle of SCLK_OUT ns
Tdsslst Output delay QSPI_SS valid after last clock edge –1 1 ns
Tdio I/O data output delay –1 1 ns
Tdin_start Input data valid start (2 + Rdelay) × Tqspi_clk – 7.52 68 ns
Tdin_end Input data valid end (2 + Rdelay) × Tqspi_clk – 1.21 68 ns
Figure 6. Quad SPI Flash Timing DiagramThis timing diagram illustrates clock polarity mode 0 and clock phase mode 0.

68 Rdelay is set by programming the register qspiregs.rddatacap. For the SoC EDS software version 13.1 and later, Intel provides automatic Quad SPI calibration in the preloader. For more information about Rdelay, refer to the Quad SPI Flash Controller chapter in the Cyclone® V Hard Processor System Technical Reference Manual.