Cyclone V Device Datasheet

ID 683801
Date 5/23/2023
Document Table of Contents

Passive Serial (PS) Configuration Timing

Table 63.  PS Timing Parameters for Cyclone® V DevicesThe specifications in this table are not applicable to Cyclone® V QS package.
Symbol Parameter Minimum Maximum Unit
tCF2CD nCONFIG low to CONF_DONE low 600 ns
tCF2ST0 nCONFIG low to nSTATUS low 600 ns
tCFG nCONFIG low pulse width 2 µs
tSTATUS nSTATUS low pulse width 268 150691 µs
tCF2ST1 nCONFIG high to nSTATUS high 150692 µs
tCF2CK 93 nCONFIG high to first rising edge on DCLK 1506 µs
tST2CK 93 nSTATUS high to first rising edge of DCLK 2 µs
tDSU DATA[] setup time before rising edge on DCLK 5.5 ns
tDH DATA[] hold time after rising edge on DCLK 0 ns
tCH DCLK high time 0.45 × 1/fMAX s
tCL DCLK low time 0.45 × 1/fMAX s
tCLK DCLK period 1/fMAX s
fMAX DCLK frequency 125 MHz
tCD2UM CONF_DONE high to user mode94 175 437 µs
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit × CLKUSR period)
Tinit Number of clock cycles required for device initialization 8,576 Cycles
91 You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
92 You can obtain this value if you do not delay configuration by externally holding nSTATUS low.
93 If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
94 The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.