Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices
CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain
CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain
Typical TX VOD Setting for Cyclone® V Transceiver Channels with termination of 100 Ω
Transmitter Pre-Emphasis Levels
Transceiver Compliance Specification
HPS Clock Performance
HPS PLL Specifications
Quad SPI Flash Timing Characteristics
SPI Timing Characteristics
SD/MMC Timing Characteristics
USB Timing Characteristics
Ethernet Media Access Controller (EMAC) Timing Characteristics
I2C Timing Characteristics
NAND Timing Characteristics
Arm* Trace Timing Characteristics
UART Interface
GPIO Interface
CAN Interface
HPS JTAG Timing Specifications
POR Specifications
FPGA JTAG Configuration Timing
FPP Configuration Timing
Active Serial (AS) Configuration Timing
DCLK Frequency Specification in the AS Configuration Scheme
Passive Serial (PS) Configuration Timing
Initialization
Configuration Files
Minimum Configuration Time Estimation
Remote System Upgrades
User Watchdog Internal Oscillator Frequency Specifications
I/O Timing
Intel offers two ways to determine I/O timing—the Excel-based I/O timing and the Intel® Quartus® Prime Timing Analyzer.
Excel-based I/O timing provides pin timing performance for each device density and speed grade. The data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the link timing analysis.
The Intel® Quartus® Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete place-and-route.
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