Cyclone V Device Datasheet

ID 683801
Date 5/23/2023
Document Table of Contents

DQS Logic Block Specifications

Table 36.  DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Cyclone® V DevicesThis error specification is the absolute maximum and minimum error.
Number of DQS Delay Buffer –C6 –C7, –I7 –C8 Unit
2 40 80 80 ps