Cyclone V Device Datasheet

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ID 683801
Date 5/23/2023
Public
Document Table of Contents
Document Table of Contents x
Cyclone V Device Datasheet
Cyclone V Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for Cyclone® V Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications OCT Variation after Power-Up Calibration Pin Capacitance Hot Socketing Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Differential HSTL and HSUL I/O Standards Differential I/O Standard Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance HPS Specifications
Transceiver Performance Specifications x
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain Typical TX VOD Setting for Cyclone® V Transceiver Channels with termination of 100 Ω Transmitter Pre-Emphasis Levels Transceiver Compliance Specification
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Performance Specifications Memory Block Performance Specifications
Periphery Performance x
High-Speed I/O Specifications DLL Frequency Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications Duty Cycle Distortion (DCD) Specifications
HPS Specifications x
HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Arm* Trace Timing Characteristics UART Interface GPIO Interface CAN Interface HPS JTAG Timing Specifications
HPS PLL Specifications x
HPS PLL VCO Frequency Range HPS PLL Input Clock Range HPS PLL Input Jitter
Configuration Specifications x
POR Specifications FPGA JTAG Configuration Timing FPP Configuration Timing Active Serial (AS) Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme Passive Serial (PS) Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Oscillator Frequency Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
I/O Timing x
Programmable IOE Delay Programmable Output Buffer Delay
Cyclone V Device Datasheet

Configuration Files

Table 65.  Uncompressed .rbf Sizes for Cyclone® V Devices

Use this table to estimate the file size before design compilation. Different configuration file formats, such as a hexadecimal file (.hex) or tabular text file (.ttf) format, have different file sizes.

For the different types of configuration file and file sizes, refer to the Intel® Quartus® Prime software. However, for a specific version of the Intel® Quartus® Prime software, any design targeted for the same device has the same uncompressed configuration file size.

The IOCSR raw binary file (.rbf) size is specifically for the Configuration via Protocol (CvP) feature.

Variant Member Code Configuration .rbf Size (bits) IOCSR .rbf Size (bits) Recommended EPCQ Serial Configuration Device96
Cyclone® V E 97 A2 21,061,280 275,608 EPCQ64
A4 21,061,280 275,608 EPCQ64
A5 33,958,560 322,072 EPCQ128
A7 56,167,552 435,288 EPCQ128
A9 102,871,776 400,408 EPCQ256
Cyclone® V GX C3 14,510,912 320,280 EPCQ32
C4 33,958,560 322,072 EPCQ128
C5 33,958,560 322,072 EPCQ128
C7 56,167,552 435,288 EPCQ128
C9 102,871,776 400,408 EPCQ256
Cyclone® V GT D5 33,958,560 322,072 EPCQ128
D7 56,167,552 435,288 EPCQ128
D9 102,871,776 400,408 EPCQ256
Cyclone® V SE 97 A2 33,958,560 322,072 EPCQ128
A4 33,958,560 322,072 EPCQ128
A5 56,057,632 324,888 EPCQ128
A6 56,057,632 324,888 EPCQ128
Cyclone® V SX C2 33,958,560 322,072 EPCQ128
C4 33,958,560 322,072 EPCQ128
C5 56,057,632 324,888 EPCQ128
C6 56,057,632 324,888 EPCQ128
Cyclone® V ST D5 56,057,632 324,888 EPCQ128
D6 56,057,632 324,888 EPCQ128
96 The recommended EPCQ serial configuration devices are able to store more than one image.
97 No PCIe* hard IP, configuration via protocol (CvP) is not supported in this family.
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