Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain Typical TX VOD Setting for Cyclone® V Transceiver Channels with termination of 100 Ω Transmitter Pre-Emphasis Levels Transceiver Compliance Specification
HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Arm* Trace Timing Characteristics UART Interface GPIO Interface CAN Interface HPS JTAG Timing Specifications
POR Specifications FPGA JTAG Configuration Timing FPP Configuration Timing Active Serial (AS) Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme Passive Serial (PS) Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Oscillator Frequency Specifications
Internal Weak Pull-Up Resistor
All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up.
|RPU||Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option.||VCCIO = 3.3 ±5%||25||kΩ|
|VCCIO = 3.0 ±5%||25||kΩ|
|VCCIO = 2.5 ±5%||25||kΩ|
|VCCIO = 1.8 ±5%||25||kΩ|
|VCCIO = 1.5 ±5%||25||kΩ|
|VCCIO = 1.35 ±5%||25||kΩ|
|VCCIO = 1.25 ±5%||25||kΩ|
|VCCIO = 1.2 ±5%||25||kΩ|
16 Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
17 Valid with ±10% tolerances to cover changes over PVT.
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