Cyclone V Device Datasheet

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ID 683801
Date 5/23/2023
Public
Document Table of Contents
Document Table of Contents x
Cyclone V Device Datasheet
Cyclone V Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for Cyclone® V Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications OCT Variation after Power-Up Calibration Pin Capacitance Hot Socketing Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Differential HSTL and HSUL I/O Standards Differential I/O Standard Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance HPS Specifications
Transceiver Performance Specifications x
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain Typical TX VOD Setting for Cyclone® V Transceiver Channels with termination of 100 Ω Transmitter Pre-Emphasis Levels Transceiver Compliance Specification
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Performance Specifications Memory Block Performance Specifications
Periphery Performance x
High-Speed I/O Specifications DLL Frequency Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications Duty Cycle Distortion (DCD) Specifications
HPS Specifications x
HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Arm* Trace Timing Characteristics UART Interface GPIO Interface CAN Interface HPS JTAG Timing Specifications
HPS PLL Specifications x
HPS PLL VCO Frequency Range HPS PLL Input Clock Range HPS PLL Input Jitter
Configuration Specifications x
POR Specifications FPGA JTAG Configuration Timing FPP Configuration Timing Active Serial (AS) Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme Passive Serial (PS) Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Oscillator Frequency Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
I/O Timing x
Programmable IOE Delay Programmable Output Buffer Delay
Cyclone V Device Datasheet

High-Speed I/O Specifications

Table 34.  High-Speed I/O Specifications for Cyclone® V Devices

When J = 1 or 2, bypass the serializer/deserializer (SERDES) block.

For LVDS applications, you must use the PLLs in integer PLL mode. This is achieved by using the LVDS clock network.

The Cyclone® V devices support the following output standards using true LVDS output buffer types on all I/O banks.

  • True RSDS output standard with data rates of up to 360 Mbps
  • True mini-LVDS output standard with data rates of up to 400 Mbps
Symbol Condition –C6 –C7, –I7 –C8, –A7 Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK_in (input clock frequency) True Differential I/O Standards Clock boost factor W = 1 to 40 63 5 — 437.5 5 — 420 5 — 320 MHz
fHSCLK_in (input clock frequency) Single-Ended I/O Standards Clock boost factor W = 1 to 4063 5 — 320 5 — 320 5 — 275 MHz
fHSCLK_OUT (output clock frequency) — 5 — 420 5 — 370 5 — 320 MHz
Transmitter True Differential I/O Standards - fHSDR (data rate) SERDES factor J =4 to 10 64 65 — 840 65 — 740 65 — 640 Mbps
SERDES factor J = 1 to 2, uses DDR registers 65 — 66 65 — 66 65 — 66 Mbps
Emulated Differential I/O Standards with Three External Output Resistor Networks- fHSDR (data rate) 67 SERDES factor J = 4 to 10 65 — 640 65 — 640 65 — 550 Mbps
Emulated Differential I/O Standards with One External Output Resistor Network - fHSDR (data rate) SERDES factor J = 4 to 10 65 — 170 65 — 170 65 — 170 Mbps
tx Jitter -True Differential I/O Standards67 Total Jitter for Data Rate, 600 Mbps – 840 Mbps — — 350 — — 380 — — 500 ps
Total Jitter for Data Rate < 600Mbps — — 0.21 — — 0.23 — — 0.30 UI
tx Jitter -Emulated Differential I/O Standards with Three External Output Resistor Networks Total Jitter for Data Rate < 640Mbps — — 500 — — 500 — — 500 ps
tx Jitter -Emulated Differential I/O Standards with One External Output Resistor Network Total Jitter for Data Rate < 640Mbps — — 0.15 — — 0.15 — — 0.15 UI
tDUTY TX output clock duty cycle for both True and Emulated Differential I/O Standards 45 50 55 45 50 55 45 50 55 %
tRISE and tFALL True Differential I/O Standards — — 200 — — 200 — — 200 ps
Emulated Differential I/O Standards with Three External Output Resistor Networks — — 250 — — 250 — — 300 ps
Emulated Differential I/O Standards with One External Output Resistor Network — — 300 — — 300 — — 300 ps
TCCS True Differential I/O Standards — — 200 — — 250 — — 250 ps
Emulated Differential I/O Standards with Three External Output Resistor Networks — — 300 — — 300 — — 300 ps
Emulated Differential I/O Standards with One External Output Resistor Network — — 300 — — 300 — — 300 ps
Receiver fHSDR (data rate) SERDES factor J =4 to 1064 65 — 87567 65 — 84067 65 — 64067 Mbps
SERDES factor J = 1 to 2, uses DDR registers 65 — 66 65 — 66 65 — 66 Mbps
Sampling Window — — — 350 — — 350 — — 350 ps
63 Clock boost factor (W) is the ratio between the input data rate and the input clock rate.
64 The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis.
65 The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
66 The maximum ideal data rate is the SERDES factor (J) × PLL max output frequency (fout), provided you can close the design timing and the signal integrity simulation is clean. You can estimate the achievable maximum data rate by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
67 You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.
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