Visible to Intel only — GUID: mcn1423234733983
Ixiasoft
Visible to Intel only — GUID: mcn1423234733983
Ixiasoft
Memory Block Performance Specifications
To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel® Quartus® Prime software to report timing for the memory block clocking schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.
Memory | Mode | Resources Used | Performance | Unit | |||
---|---|---|---|---|---|---|---|
ALUTs | Memory | –C6 | –C7, –I7 | –C8, –A7 | |||
MLAB | Single port, all supported widths | 0 | 1 | 420 | 350 | 300 | MHz |
Simple dual-port, all supported widths | 0 | 1 | 420 | 350 | 300 | MHz | |
Simple dual-port with read and write at the same address | 0 | 1 | 340 | 290 | 240 | MHz | |
ROM, all supported width | 0 | 1 | 420 | 350 | 300 | MHz | |
M10K Block | Single-port, all supported widths | 0 | 1 | 315 | 275 | 240 | MHz |
Simple dual-port, all supported widths | 0 | 1 | 315 | 275 | 240 | MHz | |
Simple dual-port with the read-during-write option set to Old Data, all supported widths | 0 | 1 | 275 | 240 | 180 | MHz | |
True dual port, all supported widths | 0 | 1 | 315 | 275 | 240 | MHz | |
ROM, all supported widths | 0 | 1 | 315 | 275 | 240 | MHz |