Cyclone V Device Datasheet

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ID 683801
Date 11/27/2019
Public
Document Table of Contents
Document Table of Contents
Cyclone V Device Datasheet
Cyclone V Device Datasheet
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for Cyclone® V Device Datasheet
Electrical Characteristics
Operating Conditions
Operating Conditions
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications OCT Variation after Power-Up Calibration Pin Capacitance Hot Socketing Internal Weak Pull-Up Resistor
I/O Standard Specifications
Single-Ended I/O Standards Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Differential HSTL and HSUL I/O Standards Differential I/O Standard Specifications
Switching Characteristics
Transceiver Performance Specifications Core Performance Specifications Periphery Performance HPS Specifications
Transceiver Performance Specifications
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain Typical TX VOD Setting for Cyclone® V Transceiver Channels with termination of 100 Ω Transmitter Pre-Emphasis Levels Transceiver Compliance Specification
Core Performance Specifications
Clock Tree Specifications PLL Specifications DSP Block Performance Specifications Memory Block Performance Specifications
Periphery Performance
High-Speed I/O Specifications DLL Frequency Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications Duty Cycle Distortion (DCD) Specifications
HPS Specifications
HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Arm* Trace Timing Characteristics UART Interface GPIO Interface CAN Interface HPS JTAG Timing Specifications
HPS PLL Specifications
HPS PLL VCO Frequency Range HPS PLL Input Clock Range HPS PLL Input Jitter
Configuration Specifications
POR Specifications FPGA JTAG Configuration Timing FPP Configuration Timing Active Serial (AS) Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme Passive Serial (PS) Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Oscillator Frequency Specifications
FPP Configuration Timing
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
I/O Timing
Programmable IOE Delay Programmable Output Buffer Delay
Cyclone V Device Datasheet

Memory Block Performance Specifications

To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel® Quartus® Prime software to report timing for the memory block clocking schemes.

When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.

Table 33.  Memory Block Performance Specifications for Cyclone® V Devices
Memory Mode Resources Used Performance Unit
ALUTs Memory –C6 –C7, –I7 –C8, –A7
MLAB Single port, all supported widths 0 1 420 350 300 MHz
Simple dual-port, all supported widths 0 1 420 350 300 MHz
Simple dual-port with read and write at the same address 0 1 340 290 240 MHz
ROM, all supported width 0 1 420 350 300 MHz
M10K Block Single-port, all supported widths 0 1 315 275 240 MHz
Simple dual-port, all supported widths 0 1 315 275 240 MHz
Simple dual-port with the read-during-write option set to Old Data, all supported widths 0 1 275 240 180 MHz
True dual port, all supported widths 0 1 315 275 240 MHz
ROM, all supported widths 0 1 315 275 240 MHz
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