Cyclone V Device Datasheet

ID 683801
Date 11/27/2019
Public
Document Table of Contents

SPI Timing Characteristics

Table 44.  SPI Master Timing Requirements for Cyclone® V DevicesThe setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode.
Symbol Description Min Max Unit
Tclk CLK clock period 16.67 ns
Tsu SPI Master-in slave-out (MISO) setup time 8.35 69 ns
Th SPI MISO hold time 1 ns
Tdutycycle SPI_CLK duty cycle 45 55 %
Tdssfrst Output delay SPI_SS valid before first clock edge 8 ns
Tdsslst Output delay SPI_SS valid after last clock edge 8 ns
Tdio Master-out slave-in (MOSI) output delay –1 1 ns
Figure 7. SPI Master Timing Diagram


Table 45.  SPI Slave Timing Requirements for Cyclone® V DevicesThe setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode.
Symbol Description Min Max Unit
Tclk CLK clock period 20 ns
Ts MOSI Setup time 5 ns
Th MOSI Hold time 5 ns
Tsuss Setup time SPI_SS valid before first clock edge 8 ns
Thss Hold time SPI_SS valid after last clock edge 8 ns
Td MISO output delay 6 ns
Figure 8. SPI Slave Timing Diagram


69 This value is based on rx_sample_dly = 1 and spi_m_clk = 120 MHz. spi_m_clk is the internal clock that is used by SPI Master to derive it’s SCLK_OUT. These timings are based on rx_sample_dly of 1. This delay can be adjusted as needed to accommodate slower response times from the slave. Note that a delay of 0 is not allowed. The setup time can be used as a reference starting point. It is very crucial to do a calibration to get the correct rx_sample_dly value because each SPI slave device may have different output delay and each application board may have different path delay. For more information about rx_sample_delay, refer to the SPI Controller chapter in the Hard Processor System Technical Reference Manual.

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