Cyclone V Device Datasheet

ID 683801
Date 11/27/2019
Public
Document Table of Contents

Programmable Output Buffer Delay

Table 70.  Programmable Output Buffer Delay for Cyclone® V Devices

This table lists the delay chain settings that control the rising and falling edge delays of the output buffer.

You can set the programmable output buffer delay in the Intel® Quartus® Prime software by setting the Output Buffer Delay Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the Output Buffer Delay assignment.

Symbol Parameter Typical Unit
DOUTBUF Rising and/or falling edge delay 0 (default) ps
50 ps
100 ps
150 ps

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