Cyclone V Device Datasheet

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ID 683801
Date 5/23/2023
Public
Document Table of Contents
Document Table of Contents x
Cyclone V Device Datasheet
Cyclone V Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for Cyclone® V Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications OCT Variation after Power-Up Calibration Pin Capacitance Hot Socketing Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Differential HSTL and HSUL I/O Standards Differential I/O Standard Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance HPS Specifications
Transceiver Performance Specifications x
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain Typical TX VOD Setting for Cyclone® V Transceiver Channels with termination of 100 Ω Transmitter Pre-Emphasis Levels Transceiver Compliance Specification
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Performance Specifications Memory Block Performance Specifications
Periphery Performance x
High-Speed I/O Specifications DLL Frequency Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications Duty Cycle Distortion (DCD) Specifications
HPS Specifications x
HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Arm* Trace Timing Characteristics UART Interface GPIO Interface CAN Interface HPS JTAG Timing Specifications
HPS PLL Specifications x
HPS PLL VCO Frequency Range HPS PLL Input Clock Range HPS PLL Input Jitter
Configuration Specifications x
POR Specifications FPGA JTAG Configuration Timing FPP Configuration Timing Active Serial (AS) Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme Passive Serial (PS) Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Oscillator Frequency Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
I/O Timing x
Programmable IOE Delay Programmable Output Buffer Delay
Cyclone V Device Datasheet

Active Serial (AS) Configuration Timing

Table 60.  AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone® V Devices (For Non Cyclone® V QS Packages)

The minimum and maximum numbers apply to both the internal oscillator and CLKUSR when either one is used as the clock source for device configuration.

The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS Timing Parameters for Cyclone® V Devices table. You can obtain the tCF2ST1 value if you do not delay configuration by externally holding nSTATUS low.

Symbol Parameter Condition Minimum Maximum Unit
tCO 86 DCLK falling edge to the AS_DATA[3:0]/ASDO output — — 2 ns
tSU 87 Data setup time before the falling edge on DCLK — 1.5 — ns
tDH 87 Data hold time after the falling edge on DCLK –6 speed grade 2.3 88 — ns
–7 or –8 speed grades 2.989/2.788 — ns
tCD2UM CONF_DONE high to user mode — 175 437 µs
tCD2CU CONF_DONE high to CLKUSR enabled — 4 × maximum DCLK period — —
tCD2UMC CONF_DONE high to user mode with CLKUSR option on — tCD2CU + (Tinit × CLKUSR period) — —
Tinit Number of clock cycles required for device initialization — 8,576 — Cycles
Table 61.  AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone® V Devices (For Cyclone® V QS Package)

The minimum and maximum numbers apply to both the internal oscillator and CLKUSR when either one is used as the clock source for device configuration.

The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS Timing Parameters for Cyclone® V Devices table. You can obtain the tCF2ST1 value if you do not delay configuration by externally holding nSTATUS low.

Symbol Parameter Condition Minimum Maximum Unit
tCO DCLK falling edge to the AS_DATA[3:0]/ASDO output — –1.3 0 ns
tSU Data setup time before the falling edge on DCLK — 2.9 — ns
tDH Data hold time after the falling edge on DCLK –6 speed grade 0.588 — ns
–7 or –8 speed grades 1.390/1.188 — ns
tCD2UM CONF_DONE high to user mode — 175 437 µs
tCD2CU CONF_DONE high to CLKUSR enabled — 4 × maximum DCLK period — —
tCD2UMC CONF_DONE high to user mode with CLKUSR option on — tCD2CU + (Tinit × CLKUSR period) — —
Tinit Number of clock cycles required for device initialization — 8,576 — Cycles
Related Information
86 Load capacitance for DCLK = 6 pF and AS_DATA/ASDO = 8 pF. Intel recommends obtaining the tCO for a given link (including receiver, transmission lines, connectors, termination resistors, and other components) through IBIS or HSPICE simulation.
87 To evaluate the data setup (tSU) and data hold time (tDH) slack on your board in order to ensure you are meeting the tSU and tDH requirement, Intel recommends following the guideline in the "Evaluating Data Setup and Hold Timing Slack" chapter in AN822: Intel FPGA Configuration Device Migration Guideline.
88 Specification for the commercial grade devices.
89 Specification for the industrial and automotive grade devices.
90 Specification for the industrial grade devices.
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