Cyclone V Device Datasheet

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ID 683801
Date 5/23/2023
Public
Document Table of Contents
Document Table of Contents x
Cyclone V Device Datasheet
Cyclone V Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for Cyclone® V Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications OCT Variation after Power-Up Calibration Pin Capacitance Hot Socketing Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Differential HSTL and HSUL I/O Standards Differential I/O Standard Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance HPS Specifications
Transceiver Performance Specifications x
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain Typical TX VOD Setting for Cyclone® V Transceiver Channels with termination of 100 Ω Transmitter Pre-Emphasis Levels Transceiver Compliance Specification
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Performance Specifications Memory Block Performance Specifications
Periphery Performance x
High-Speed I/O Specifications DLL Frequency Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications Duty Cycle Distortion (DCD) Specifications
HPS Specifications x
HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Arm* Trace Timing Characteristics UART Interface GPIO Interface CAN Interface HPS JTAG Timing Specifications
HPS PLL Specifications x
HPS PLL VCO Frequency Range HPS PLL Input Clock Range HPS PLL Input Jitter
Configuration Specifications x
POR Specifications FPGA JTAG Configuration Timing FPP Configuration Timing Active Serial (AS) Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme Passive Serial (PS) Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Oscillator Frequency Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
I/O Timing x
Programmable IOE Delay Programmable Output Buffer Delay
Cyclone V Device Datasheet

HPS Power Supply Operating Conditions

Table 6.  HPS Power Supply Operating Conditions for Cyclone® V SX and ST DevicesThis table lists the steady-state voltage and current values expected from Cyclone® V system-on-a-chip (SoC) devices with Arm* -based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to the Recommended Operating Conditions for Cyclone® V Devices table for the steady-state voltage values expected from the FPGA portion of the Cyclone® V SoC devices.
Symbol Description Condition Minimum 11 Typical Maximum11 Unit
VCC_HPS HPS core voltage and periphery circuitry power supply — 1.07 1.1 1.13 V
VCCPD_HPS 12 HPS I/O pre-driver power supply 3.3 V 3.135 3.3 3.465 V
3.0 V 2.85 3.0 3.15 V
2.5 V 2.375 2.5 2.625 V
VCCIO_HPS HPS I/O buffers power supply 3.3 V 3.135 3.3 3.465 V
3.0 V 2.85 3.0 3.15 V
2.5 V 2.375 2.5 2.625 V
1.8 V 1.71 1.8 1.89 V
1.5 V 1.425 1.5 1.575 V
1.35 V 13 1.283 1.35 1.418 V
1.2 V 1.14 1.2 1.26 V
VCCRSTCLK_HPS HPS reset and clock input pins power supply 3.3 V 3.135 3.3 3.465 V
3.0 V 2.85 3.0 3.15 V
2.5 V 2.375 2.5 2.625 V
1.8 V 1.71 1.8 1.89 V
VCCPLL_HPS HPS PLL analog voltage regulator power supply — 2.375 2.5 2.625 V
VCC_AUX_SHARED 14 HPS auxiliary power supply — 2.375 2.5 2.625 V
Related Information
11 The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
12 VCCPD_HPS must be 2.5 V when VCCIO_HPS is 2.5, 1.8, 1.5, or 1.2 V. VCCPD_HPS must be 3.0 V when VCCIO_HPS is 3.0 V. VCCPD_HPS must be 3.3 V when VCCIO_HPS is 3.3 V.
13 VCCIO_HPS 1.35 V is supported for HPS row I/O bank only.
14 VCC_AUX_SHARED must be powered by the same source as VCC_AUX for Cyclone® V SX C5, C6, D5, and D6 devices, and Cyclone® V SE A5 and A6 devices.
Level Two Title