Cyclone V Device Datasheet

ID 683801
Date 11/27/2019
Public
Document Table of Contents

Ethernet Media Access Controller (EMAC) Timing Characteristics

Table 48.  Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Cyclone® V Devices
Symbol Description Min Typ Max Unit
Tclk (1000Base-T) TX_CLK clock period 8 ns
Tclk (100Base-T) TX_CLK clock period 40 ns
Tclk (10Base-T) TX_CLK clock period 400 ns
Tdutycycle TX_CLK duty cycle 45 55 %
Td TX_CLK to TXD/TX_CTL output data delay –0.85 0.15 ns
Figure 11. RGMII TX Timing Diagram


Table 49.  RGMII RX Timing Requirements for Cyclone® V Devices
Symbol Description Min Typ Unit
Tclk (1000Base-T) RX_CLK clock period 8 ns
Tclk (100Base-T) RX_CLK clock period 40 ns
Tclk (10Base-T) RX_CLK clock period 400 ns
Tsu RX_D/RX_CTL setup time 1 ns
Th RX_D/RX_CTL hold time 1 ns
Figure 12. RGMII RX Timing Diagram


Table 50.  Management Data Input/Output (MDIO) Timing Requirements for Cyclone® V Devices
Symbol Description Min Typ Max Unit
Tclk MDC clock period 400 ns
Td MDC to MDIO output data delay 10 20 ns
Ts Setup time for MDIO data 10 ns
Th Hold time for MDIO data 0 ns
Figure 13. MDIO Timing Diagram


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