Cyclone V Device Datasheet

ID 683801
Date 11/27/2019
Document Table of Contents

HPS JTAG Timing Specifications

Table 54.  HPS JTAG Timing Parameters and Values for Cyclone® V Devices
Symbol Description Min Max Unit
tJCP TCK clock period 30 ns
tJCH TCK clock high time 14 ns
tJCL TCK clock low time 14 ns
tJPSU (TDI) TDI JTAG port setup time 2 ns
tJPSU (TMS) TMS JTAG port setup time 3 ns
tJPH JTAG port hold time 5 ns
tJPCO JTAG port clock to output 12 73 ns
tJPZX JTAG port high impedance to valid output 1473 ns
tJPXZ JTAG port valid output to high impedance 1473 ns
73 A 1-ns adder is required for each VCCIO _HPS voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO _HPS of the TDO I/O bank = 2.5 V, or 14 ns if it equals 1.8 V.

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