Cyclone V Device Datasheet

ID 683801
Date 5/23/2023
Document Table of Contents

SD/MMC Timing Characteristics

Table 46.  Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Cyclone® V Devices

After power up or cold reset, the Boot ROM uses drvsel = 3 and smplsel = 0 to execute the code. At the same time, the SD/MMC controller enters the Identification Phase followed by the Data Phase. During this time, the value of interface output clock SDMMC_CLK_OUT changes from a maximum of 400 kHz (Identification Phase) up to a maximum of 12.5 MHz (Data Phase), depending on the internal reference clock SDMMC_CLK and the CSEL setting. The value of SDMMC_CLK is based on the external oscillator frequency and has a maximum value of 50 MHz.

After the Boot ROM code exits and control is passed to the preloader, software can adjust the value of drvsel and smplsel via the system manager. drvsel can be set from 1 to 7 and smplsel can be set from 0 to 7. While the preloader is executing, the values for SDMMC_CLK and SDMMC_CLK_OUT increase to a maximum of 200 MHz and 50 MHz respectively.

Symbol Description Min Max Unit
Tsdmmc_clk (internal reference clock) SDMMC_CLK clock period (Identification mode) 20 ns
SDMMC_CLK clock period (Default speed mode) 5 ns
SDMMC_CLK clock period (High speed mode) 5 ns
Tsdmmc_clk_out (interface output clock) SDMMC_CLK_OUT clock period (Identification mode) 2500 ns
SDMMC_CLK_OUT clock period (Default speed mode) 40 ns
SDMMC_CLK_OUT clock period (High speed mode) 20 ns
Tdutycycle SDMMC_CLK_OUT duty cycle 45 55 %
Td SDMMC_CMD/SDMMC_D output delay (Tsdmmc_clk × drvsel)/2 – 1.23 70 (Tsdmmc_clk × drvsel)/2 + 1.69 70 ns
Tsu Input setup time 1.05 – (Tsdmmc_clk × smplsel)/2 71 ns
Th Input hold time (Tsdmmc_clk × smplsel)/2 71 ns
Figure 9. SD/MMC Timing Diagram

70 drvsel is the drive clock phase shift select value.
71 smplsel is the sample clock phase shift select value.