Tsdmmc_clk (internal reference clock) |
SDMMC_CLK clock period (Identification mode) |
20 |
— |
ns |
SDMMC_CLK clock period (Default speed mode) |
5 |
— |
ns |
SDMMC_CLK clock period (High speed mode) |
5 |
— |
ns |
Tsdmmc_clk_out (interface output clock) |
SDMMC_CLK_OUT clock period (Identification mode) |
2500 |
— |
ns |
SDMMC_CLK_OUT clock period (Default speed mode) |
40 |
— |
ns |
SDMMC_CLK_OUT clock period (High speed mode) |
20 |
— |
ns |
Tdutycycle |
SDMMC_CLK_OUT duty cycle |
45 |
55 |
% |
Td |
SDMMC_CMD/SDMMC_D output delay |
(Tsdmmc_clk × drvsel)/2 – 1.23 70 |
(Tsdmmc_clk × drvsel)/2 + 1.69 70 |
ns |
Tsu |
Input setup time |
1.05 – (Tsdmmc_clk × smplsel)/2 71 |
— |
ns |
Th |
Input hold time |
(Tsdmmc_clk × smplsel)/2 71 |
— |
ns |