The Sequencer Monitor is able to decode up to 16 Avalon® Streaming ( Avalon® -ST) ADC interfaces. Depending on which device you choose, each Avalon® -ST ADC interface can contain voltage levels of up to nine or 17 analog input channels. The sequencer allows a total of 144 monitored voltage levels.

The decoder allows you to map any of the voltage level busses or external POK signals to any monitored VOUT or VIN rail. The configurable options allow you to specify the number of VOUT rails, the number of ADC interfaces, the number of power good inputs (POK signals), and how long to debounce both the power good or analog inputs.

The debouncer passes through the POK signal only after it has been stable for the duration of the debounce interval. You can select from 28 levels of debounce. The duration of the interval depends on the clock frequency that you provide to the component.

The progression of the debounce level is exponential in time. The parameter editor of the Sequencer Monitor component calculates the debounce duration only after the clock of the component connects to the system clock in Platform Designer. Otherwise, the parameter editor does not make any calculation and the Component’s Clock Frequency box displays 0 MHz.

For every VIN and VOUT rail, you can select the source for the ADC Interface/PG input and the ADC/PG Channel. Typically, select a unique interface and channel combination for each rail. If you set multiple rails to the same combination, the parameter editor displays a warning message. However, the Quartus® Prime software still allows you to generate the system if that is what you want.

Analog inputs are debounced by specifying how many ADC samples to check before declaring a warning or fault. To prevent false errors or warnings that may be caused by noise on monitored voltage rails, specify the ADC Samples to Check parameter. The design only reports an error or warning condition if the condition is present for the number of samples you specify in this parameter.

The interval duration depends on the sample rate and sequencer configuration in the ADC. For example, assume that you configure the Modular ADC Core IP sequencer to process the inputs in a round-robin fashion, reporting the voltage levels for each channel in sequence over seven time slots. If the sample rate is 1 MSPS and you configure the Sequencer Monitor component to check that five samples exceed the threshold before declaring a warning or error, then the warning or error must be present for $1\text{\hspace{0.17em}μs}\times 7\text{\hspace{0.17em}time slots}\times 5\text{\hspace{0.17em}samples}=35\text{\hspace{0.17em}μs}$.

Options for Functionality Level and Error Logging Level control the overall implementation size of the sequencer and are discussed in the Sequencer Monitor Parameters table below.

If an ADC VIN pin monitors a rail, either one of these settings determines the rail’s power good status:

• The levels set in the default configuration of the Sequencer Monitor within the Platform Designer (specified as a percentage of the rail's typical voltage).
• The dynamically modified levels set through the PMBus* interface.

The Power Sequencer component uses the power good status outputs from the Voltage Monitor to sequence the power regulators on or off.

The following PMBus* commands dynamically adjust the levels to assert or deassert the internal power good signal:

• VIN_ON and VIN_OFF commands dynamically adjust the levels at which the internal power good status is asserted or removed for VIN.
• POWER_GOOD_ON and POWER_GOOD_OFF commands dynamically adjust the levels at which the internal power good status is asserted or removed for VOUT.

The following thresholds provide you with a comprehensive monitoring approach to safely track all input and output voltages and allow you to automatically or manually sequence a power down of the rails in case of an error:

• Undervoltage warning
• Undervoltage fault
• Overvoltage warning
• Overvoltage fault

When the rail is defined as a Power Good input in the Channel Decoder tab, the Voltage Monitor threshold settings are inapplicable and not displayed, as shown the following figure.

After the system enables the voltage rail and its level rises, the rail transitions through the undervoltage fault region and into the power good region. While power good is not asserted, the design masks all voltage faults for a given rail so that this portion of the ramp up cycle is not marked as a fault.

After the system reaches the power good level, the rail is still in a state that causes undervoltage warning reports. This behavior is normal and expected. It is possible that the PMBus* may report undervoltage warnings for some of the rails depending on ADC sample rates and the rise time of the rail. This can be masked out by increasing the ADC Samples to Check parameter, or simply cleared out as a function of your board management control operation.

Once the rail reaches its nominal voltage, send the CLEAR_FAULTS command to clear out any latched warnings in the VOUT status registers. You can safely ignore these latched warnings. At this point, the system should be in a normal operation state.

If the rail drifts outside the typical operating range for longer than the duration set in the ADC Samples to Check parameter, the design reports overvoltage or undervoltage warnings. The warning causes assertion of the SMB_ALERTN pin. If no other devices are asserting SMB_ALERTN at this time, the page associated with the warning also asserts STATUS_OTHER bit 0: First to Assert SMBALERT#. You can use this status to indicate which rail was the first to experience an error. If the rail exceeds the levels for an overvoltage or undervoltage fault for longer than the duration specified in the ADC Samples to Check parameter, the system behaves according to the programmed response.

In the Voltage Monitor Settings tab, there are independent checkboxes for each rail. These independent settings allow you to specify a controlled automatic power down sequence in case of overvoltage or undervoltage faults. You can adjust these responses dynamically with the PMBus* commands VIN_OV_FAULT_RESP, VIN_UV_FAULT_RESP, VOUT_OV_FAULT_RESP, and VOUT_UV_FAULT_RESP.

The sequencer supports four different behaviors for a fault:

• Ignore that fault and continue operation
• Sequence an immediate power down
• Retry for a selectable number of times from one to six attempts
• Retry indefinitely

The Power Sequencer component does not retry power sequencing until all power good signals for the VOUT rails are deasserted. To specify the duration between retry attempts, set the Delay Time Between Restarts parameter in the Power Sequencer component parameter editor. The timer starts after the power good signals deassert.

If a rail uses an external power good signal—typically, a POK output from a power supply—and the ADC VIN does not monitor the rail, the design passes the external power good signal directly to the sequencer. In this case, a reduced set of PMBus* commands (undervoltage response and status-related commands) are available. Loss of POK on a digitally monitored rail causes an undervoltage fault, with the selected undervoltage response.

When logging is enabled, the monitor block contains a time-of-day clock and provides the data to the non-volatile flash interface for capture:

• Error type—this is filtered, based on which of the following errors you have decided to log:
  • Qualification window timeout (occurs while the sequencer is actively sequencing up, if the rail has not reached "power good" on an analog rail, or POK is not asserted for a digital rail before the specified timeout value in the sequencer)
  • VIN undervoltage fault
  • VIN overvoltage fault
  • VOUT undervoltage fault
  • VOUT overvoltage fault
• Black Box data—the current state for all digital and analog rails
• Timestamp—the current time of day, as reported by the internal clock

The time-of-day clock requires software initialization upon startup, and the MFR_TOD command indicates the number of seconds counted since 1/1/2020. Unless initialized, it indicates the number of seconds counted since power-up. It should be periodically set by software, to ensure accurate timestamps. You can adjust the value stored by the MFR_TOD_ADJUST command, in order to speed up or slow down the clock. It is initialized with the value of the reference clock and indicates the number of clock ticks per second.

Up to 32 error events can be stored in the error log. Once full, you need to issue a command to clear the log (by setting bit 0 in the MFR_NV_CONTROL command) before any new entries can be written. Specific enables are available for every fault on every page (with the MFR_NV_PAGE_EN command), as well as top-level enables (with the MFR_NV_MASTER_EN command). By default, the lower-level faults are always enabled, and the default value for the top-level enables are controlled by the Sequencer Monitor's Power-on Logging Enable parameter. In a controlled power-down, you might want to disable these top-level enables to prevent fault conditions from being logged to flash. For more details on non-volatile error logging, refer to the MAX10 OCFlash Controller (NVRAM_Controller) section.