AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

ID 683778
Date 9/30/2019
Public
Document Table of Contents

3.3.1. Pin Description

Table 8.   Power Sequencer Signals
Name Direction Type Description
CLOCK Input 3.3 V LVTTL Free-running global clock that the design uses as a timing reference for calculated delays.
ENABLE Input 3.3 V Schmitt Trigger

Master enable signal:

  • When asserted—allows power up sequencing
  • When deasserted—sequences all power regulators down
VIN_FAULT Input 3.3 V Schmitt Trigger

Indicates an external fault has occurred.

When asserted, the design sequences all power regulators down.

VRAIL_PWRGD[N:0] Input 3.3 V Schmitt Trigger with WEAK_PULL_UP Power good indication from the power supply of each rail.
VRAIL_ENA[N:0] Output 3.3 V LVTTL Enable signal for the power supply of each rail.
VRAIL_DCHG[N:0] Output 3.3 V LVTTL Discharge signal for the discharge Field-Effect Transistor (FET) on each rail.
nFAULT Output 3.3 V LVTTL Indicates that the sequencer has detected a fault and is sequencing all power rails down.
VRAIL_MON[N:0] Input 3.3 V LVTTL

Externally scaled voltage monitor for VOUT power supplies.

This input is not present at the top level but the ADC directly connects it.

VIN_MON Input 3.3 V LVTTL

Externally scaled voltage monitor for VIN power supplies.

This input is not present at the top level but the ADC directly connects it.

SMB_SCL Input 3.3 V LVTTL, Open Drain PMBus* serial clock line generated by the PMBus* master.
SMB_SDA Bidir 3.3 V LVTTL, Open Drain

PMBus* serial data line.

In transmit mode, this pin is open drain. The design acquires data on the positive edge, and delivers data on the negative edge of the PMBus* serial clock line.

SMB_ALERTN Output 3.3 V LVTTL, Open Drain PMBus Alarm Indication.

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