AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

Download
ID 683778
Date 9/30/2019
Public
Document Table of Contents
Document Table of Contents
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design 2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design 3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design 4. Functionality Level and Resource Utilization Estimates 5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design 6. Document Revision History for AN 896: Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design
1.1. Features of the Reference Design 1.2. Structure of the Reference Design Archive
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design
2.1. Reference Design Architecture 2.2. Reference Design Component Blocks 2.3. Design Components and Parameter Options 2.4. Output Voltage Data Formats and Related Parameters
2.3. Design Components and Parameter Options
2.3.1. Modular ADC Core Intel® FPGA IP (ADC_Core) 2.3.2. Sequencer ADC Decoder (ADC_Decoder) 2.3.3. Sequencer Voltage Monitor (Sequencer_VMonitor) 2.3.4. PMBus* Slave to Avalon®-MM Master Bridge (PMBus_Slave) 2.3.5. Power Sequencer (Sequencer_Core) 2.3.6. Other Design Components
2.3.2. Sequencer ADC Decoder (ADC_Decoder)
2.3.2.1. Sequencer ADC Decoder Parameter Settings
2.3.3. Sequencer Voltage Monitor (Sequencer_VMonitor)
2.3.3.1. Sequencer Voltage Monitor Parameter Settings
2.3.5. Power Sequencer (Sequencer_Core)
2.3.5.1. Power Sequencer Parameter Settings
2.3.6. Other Design Components
2.3.6.1. pll_lock_splitter (PLL_LockSplit) 2.3.6.2. Avalon®-MM Sequencer (AVMM_Initializer)
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design
3.1. Customizing and Generating the Design Example 3.2. Updating the Schematic After Customizing the Design 3.3. Assigning Pins and Compiling the Design Example 3.4. Testbench Simulation to Understand Design Behavior
3.3. Assigning Pins and Compiling the Design Example
3.3.1. Pin Description
3.4. Testbench Simulation to Understand Design Behavior
3.4.1. Generating the Testbench Simulation 3.4.2. Running the Testbench Simulation
4. Functionality Level and Resource Utilization Estimates
4.1. PMBus* Commands Implementation 4.2. Resource Utilization of the Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design
4. Functionality Level and Resource Utilization Estimates
5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design
6. Document Revision History for AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

3.3.1. Pin Description

Table 8.   Power Sequencer Signals
Name Direction Type Description
CLOCK Input 3.3 V LVTTL Free-running global clock that the design uses as a timing reference for calculated delays.
ENABLE Input 3.3 V Schmitt Trigger

Master enable signal:

  • When asserted—allows power up sequencing
  • When deasserted—sequences all power regulators down
VIN_FAULT Input 3.3 V Schmitt Trigger

Indicates an external fault has occurred.

When asserted, the design sequences all power regulators down.
VRAIL_PWRGD[N:0] Input 3.3 V Schmitt Trigger with WEAK_PULL_UP Power good indication from the power supply of each rail.
VRAIL_ENA[N:0] Output 3.3 V LVTTL Enable signal for the power supply of each rail.
VRAIL_DCHG[N:0] Output 3.3 V LVTTL Discharge signal for the discharge Field-Effect Transistor (FET) on each rail.
nFAULT Output 3.3 V LVTTL Indicates that the sequencer has detected a fault and is sequencing all power rails down.
VRAIL_MON[N:0] Input 3.3 V LVTTL

Externally scaled voltage monitor for VOUT power supplies.

This input is not present at the top level but the ADC directly connects it.

VIN_MON Input 3.3 V LVTTL

Externally scaled voltage monitor for VIN power supplies.

This input is not present at the top level but the ADC directly connects it.

SMB_SCL Input 3.3 V LVTTL, Open Drain PMBus* serial clock line generated by the PMBus* master.
SMB_SDA Bidir 3.3 V LVTTL, Open Drain

PMBus* serial data line.

In transmit mode, this pin is open drain. The design acquires data on the positive edge, and delivers data on the negative edge of the PMBus* serial clock line.

SMB_ALERTN Output 3.3 V LVTTL, Open Drain PMBus Alarm Indication.
Level Two Title

Did you find the information on this page useful?

Characters remaining:

Feedback Message