AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

ID 683778
Date 9/30/2019
Public
Document Table of Contents

3.3. Assigning Pins and Compiling the Design Example

After customizing the design and generating the HDL files in the Platform Designer, you can prepare and compile the design example.
  1. In the main Intel® Quartus® Prime window, with the design example project opened, click Assignments > Device from the main menu.
    Figure 16. Select the Target Device in Intel® Quartus® Prime


  2. In the Device window, select the appropriate Intel® MAX® 10 device for your system and click OK.
    If you want the sequencer to perform voltage monitoring, the device you select must have ADC support.
  3. Click Assignments > Pin Planner.
  4. In the Pin Planner window, drag pin names from the All Pins pane to the pin location on the physical representation of the device in the center of the Pin Planner window.
    Alternatively, type the pin number in the Location column of the All Pins pane.
    Figure 17. Assigning Pins in the Pin Planner Window


  5. If you change the frequencey of the reference clock to the PLL in Platform Designer, adjust the timing constraint for the reference clock input in the <installation directory>\quartus\sequencer.sdc file. Search for this line:
    create_clock -name clk_ref -period 50.0MHz [get_ports {clk}]
    For example, if you change the reference clock from 50 MHz to 25 MHz, change the line to:
    create_clock -name clk_ref -period 25.0MHz [get_ports {clk}]
  6. In the main Intel® Quartus® Prime window, click Processing > Start Compilation.
    Alternatively, click the Start Compilation icon in the main Intel® Quartus® Prime toolbar.
After the compilation completes, use the <installation directory>\quartus\output_files\sequencer.pof to program the targetted Intel® MAX® 10 device.

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