AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

ID 683778
Date 3/15/2024
Document Table of Contents

3.4.1. Generating the Testbench Simulation

The testbench system instantiates the sequencer_qsys.qsys subsystem and simple bus functional models (BFMs) for clock and reset.
  1. From the Quartus® Prime menu, click File > Open
  2. Select the <installation directory>\source\sequencer_qsys_tb.qsys file and click Open.
  3. Click Generate HDL in the Platform Designer window.
  4. In the Generation window:
    1. Select Verilog or VHDL in the Create simulation model box.
    2. Click Generate.
    Figure 19.  Platform Designer Generation Window

  5. In the Generate Completed window, click Close.
The Platform Designer generates the simulation files in the <installation directory>\source\sequencer_qsys_tb\simulation directory.