Visible to Intel only — GUID: smj1561708451291
Ixiasoft
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design
4. Functionality Level and Resource Utilization Estimates
5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design
6. Document Revision History for AN 896: Multi-Rail Power Sequencer and Monitor Reference Design
2.3.1. Reset Sequencer (Reset_Sequencer)
2.3.2. Modular ADC Core Intel® FPGA IP (ADC_Core)
2.3.3. Sequencer Monitor (Sequencer_Monitor)
2.3.4. PMBus* Slave to Avalon®-MM Master Bridge (PMBus_Slave)
2.3.5. Power Sequencer (Sequencer_Core)
2.3.6. MAX10 OCFlash Controller (NVRAM_Controller)
2.3.7. On-Chip Flash Intel® FPGA IP (NVRAM_OC_Flash)
2.3.8. Other Design Components
Visible to Intel only — GUID: smj1561708451291
Ixiasoft
4. Functionality Level and Resource Utilization Estimates
The Multi-Rail Power Sequencer and Monitor reference design allows you to customize the functionality levels. The various functionality levels affect the PMBus* command implementation and use different numbers of resources.