AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

Download PDF
ID 683778
Date 4/24/2025
Public

Visible to Intel only — GUID: eln1744855780793

Ixiasoft

View Details

Document Table of Contents
Document Table of Contents x
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design 2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design 3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design 4. Functionality Level and Resource Utilization Estimates 5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design 6. Document Revision History for AN 896: Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design x
1.1. Features of the Reference Design 1.2. Structure of the Reference Design Archive
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design x
2.1. Reference Design Architecture 2.2. Reference Design Component Blocks 2.3. Design Components and Parameter Options 2.4. Output Voltage Data Formats and Related Parameters
2.3. Design Components and Parameter Options x
2.3.1. Reset Sequencer (Reset_Sequencer) 2.3.2. Modular ADC Core Intel® FPGA IP (ADC_Core) 2.3.3. Sequencer Monitor (Sequencer_Monitor) 2.3.4. PMBus* Slave to Avalon®-MM Master Bridge (PMBus_Slave) 2.3.5. Power Sequencer (Sequencer_Core) 2.3.6. MAX10 OCFlash Controller (NVRAM_Controller) 2.3.7. On-Chip Flash Intel® FPGA IP (NVRAM_OC_Flash) 2.3.8. Other Design Components
2.3.3. Sequencer Monitor (Sequencer_Monitor) x
2.3.3.1. Sequencer Monitor Parameter Settings
2.3.5. Power Sequencer (Sequencer_Core) x
2.3.5.1. Power Sequencer Parameter Settings
2.3.6. MAX10 OCFlash Controller (NVRAM_Controller) x
2.3.6.1. MAX10 OCFlash Controller Parameter Settings
2.3.8. Other Design Components x
2.3.8.1. POR Pulse (POR_Pulse) 2.3.8.2. Reset to Conduit Adapter (Reset2Conduit) 2.3.8.3. pll_lock_splitter (PLL_LockSplit) 2.3.8.4. Avalon®-MM Sequencer (AVMM_Initializer) 2.3.8.5. Alignment Bridge (PM2AVMM_Align)
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design x
3.1. Customizing and Generating the Design Example 3.2. Updating the Schematic After Customizing the Design 3.3. Assigning Pins and Compiling the Design Example 3.4. Testbench Simulation to Understand Design Behavior 3.5. Controlling the Sequencer using System Console
3.3. Assigning Pins and Compiling the Design Example x
3.3.1. Pin Description
3.4. Testbench Simulation to Understand Design Behavior x
3.4.1. Generating the Testbench Simulation 3.4.2. Running the Testbench Simulation
3.5. Controlling the Sequencer using System Console x
3.5.1. Interacting with the Sequencer through System Console
4. Functionality Level and Resource Utilization Estimates x
4.1. PMBus* Commands Implementation 4.2. PMBus* STATUS Command Descriptions 4.3. Resource Utilization of the Multi-Rail Power Sequencer and Monitor Reference Design
4.2. PMBus* STATUS Command Descriptions x
4.2.1. STATUS_BYTE Command Description 4.2.2. STATUS_WORD Command Description 4.2.3. STATUS_VOUT Command Description 4.2.4. STATUS_INPUT Command Description 4.2.5. STATUS_CML Command Description 4.2.6. STATUS_OTHER Command Description
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design
4. Functionality Level and Resource Utilization Estimates
5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design
6. Document Revision History for AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

3.5.1. Interacting with the Sequencer through System Console

After compiling the design with the modifications described in the Controlling the Sequencer using System Console section configuring the MAX® 10 FPGA, you can connect to it with the System Console tool using the following steps:
  1. Launch the System Console tool from the Quartus® Prime software (Tools > System Debugging Tools > System Console).
  2. Click the Load Design… button, and select Sequencer.qpf (or your project's .qpf file).
  3. In the Tcl Console window, type source jtag_pmbus.tcl.
    • If you have not load the design, or do not have the JTAG bridge enabled in your design, an error message similar to the following appears:
      % source jtag_pmbus.tcl
error: claim_service: Path cannot be found
A successful connection shows an output message similar to the following: 
% source jtag_pmbus.tcl
Info: Opened JTAG Master Service: /devices/10M50DA(.|ES)|10M50DC@1#USB-1/(link)/JTAG/alt_sld_fab_sldfabric.node_0/phy_0/PM2AVMM_JTAG_Master.master
Info: Detected 4 sequencer output rails.
Once the command prompt is available, a variety of diagnostic commands are available for use. For example, to display the voltage levels for all monitored rails, you can use the READ_VOUT command: 
% READ_VOUT
Page 0 VOUT: 1.005 V
Page 1 VOUT: 1.196 V
Page 2 VOUT: Digital Rail
Page 3 VOUT: 1.799 V
You can obtain a list of available functions and their syntax by typing HELP: 
% HELP
Available commands:
  SCAN :
     Inspect the PMBus register space for the sequencer's configuration.
  CLEAR_STATUS :
     Clear out all latched status from the various status registers.
  SET_PAGE <page> :
     Specify the PMBus page register in the slave device.
  SET_RETRIES <retries> :
     Set the number of retries after an error (0-7,7=infinite).
  SET_DELAY <delay> :
     Enable/disable the timeout in the global response register.
  SET_TOD_ADJUST <value> :
     Adjust the number of clock ticks per second.
  SET_TOD :
     Sets the current Time of Day counter to system clock.
  SET_RESPONSE <page> <condition> <response>:
     Set the VIN/VOUT over/undervoltage error condition response.
     (condition=VIN_UV|VIN_OV|VOUT_UV|VOUT_OV)
     (response=0:continue without interruption, 2: sequence down)
  NVLOG_ENABLE <log_level>:
     Enables varying levels of non-volatile flash error logging
     (0=disabled, 1=errors logged, 3= errors & blackbox status).
  NVLOG_CLEAR :
     Clear out all NV Flash Entries.
  READ_TOD :
     Read the current Time of Day counter.
  READ_TOD_ADJUST :
     Read the current Time of Day adjustment counter.
  READ_NVCFG :
     Read the configuration of NV Logging stats.
  READ_NVLOG_ENTRY <entry> :
     Read an entry from the NV Log.
  READ_VOUT :
     Read the current VOUT voltage levels for all output rails.
  READ_STATUS :
     Read the current error status, and decode values via masking.
  READ_RESPONSE :
     Display how the sequencer will respond to various error conditions.
  ERROR_VOUT_UV <page> :
     Send vout undervoltage error to specified page.
  WARN_VOUT_UV <page> :
     Send vout undervoltage warning to specified page.
  WARN_VOUT_OV <page> :
     Send vout overvoltage warning to specified page.
  ERROR_VOUT_OV <page> :
     Send vout overvoltage error to specified page.
Level Two Title