The Intel® MAX® 10 analog to digital converter (ADC) block is a 12-bit successive approximation register (SAR) ADC with a one million samples per second (MSPS) sampling rate. The Modular ADC Core Intel® FPGA IP is a standard Intel® MAX® 10 IP that sequences through the various analog input channels, providing you with a 12-bit representation of the input voltage level.
Figure 5. ADC Channel ConfigurationThe configuration of the Modular ADC Core IP in the reference design uses the Standard sequencer with external sample storage core variant. In this core variant, the IP passes the sampled input directly to a streaming output interface instead of buffering the data internally.
Figure 6. ADC Sequencer ConfigurationThe configuration of the Modular ADC Core IP in the reference design sets the programmable ADC sequencer to operate in a round-robin fashion, sequencing through each of the analog inputs.
For higher accuracy, always use an external reference voltage:
- For dual-supply Intel® MAX® 10 devices, use a 2.5 V external reference voltage.
- For single-supply Intel® MAX® 10 devices, use a 3.0 V or 3.3 V external reference voltage.
To ensure that the maximum value of the power rail is within the measurable range of the ADC, use external voltage dividers on the monitored rails:
- Keep thresholds such as the overvoltage fault less than the reference voltage.
- Use resistor values that maximize the measurement accuracy by not dividing lower than necessary.