AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

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ID 683778
Date 3/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design 2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design 3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design 4. Functionality Level and Resource Utilization Estimates 5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design 6. Document Revision History for the AN 896: Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design x
1.1. Features of the Reference Design 1.2. Structure of the Reference Design Archive
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design x
2.1. Reference Design Architecture 2.2. Reference Design Component Blocks 2.3. Design Components and Parameter Options 2.4. Output Voltage Data Formats and Related Parameters
2.3. Design Components and Parameter Options x
2.3.1. Reset Sequencer (Reset_Sequencer) 2.3.2. Modular ADC Core Intel® FPGA IP (ADC_Core) 2.3.3. Sequencer ADC Decoder (ADC_Decoder) 2.3.4. Sequencer Voltage Monitor (Sequencer_VMonitor) 2.3.5. PMBus* Slave to Avalon®-MM Master Bridge (PMBus_Slave) 2.3.6. Power Sequencer (Sequencer_Core) 2.3.7. Other Design Components
2.3.3. Sequencer ADC Decoder (ADC_Decoder) x
2.3.3.1. Sequencer ADC Decoder Parameter Settings
2.3.4. Sequencer Voltage Monitor (Sequencer_VMonitor) x
2.3.4.1. Sequencer Voltage Monitor Parameter Settings
2.3.6. Power Sequencer (Sequencer_Core) x
2.3.6.1. Power Sequencer Parameter Settings
2.3.7. Other Design Components x
2.3.7.1. POR Pulse (POR_Pulse) 2.3.7.2. Reset to Conduit Adapter (Reset2Conduit) 2.3.7.3. pll_lock_splitter (PLL_LockSplit) 2.3.7.4. Avalon®-MM Sequencer (AVMM_Initializer)
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design x
3.1. Customizing and Generating the Design Example 3.2. Updating the Schematic After Customizing the Design 3.3. Assigning Pins and Compiling the Design Example 3.4. Testbench Simulation to Understand Design Behavior
3.3. Assigning Pins and Compiling the Design Example x
3.3.1. Pin Description
3.4. Testbench Simulation to Understand Design Behavior x
3.4.1. Generating the Testbench Simulation 3.4.2. Running the Testbench Simulation
4. Functionality Level and Resource Utilization Estimates x
4.1. PMBus* Commands Implementation 4.2. Resource Utilization of the Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design
4. Functionality Level and Resource Utilization Estimates
5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design
6. Document Revision History for the AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

2.3.3.1. Sequencer ADC Decoder Parameter Settings

There are two groups of options: Parameters and ADC Channel Mapping.
Table 1.   Sequencer ADC Decoder Parameters - Parameters
Parameter Description
Output Voltage Rails

Specify the number of output voltage rails to sequence.

The number must match the value you specify in the other components of the system. Otherwise, the interface bus widths between components will not match.

ADC Streaming Interfaces

Select the number of Avalon® -ST interfaces from the Sequencer ADC Decoder to the Modular ADC Core IP.

  • A single-ADC MAX® 10 device has one interface while a dual-ADC MAX® 10 device has two Avalon® -ST interfaces.
  • If you use several MAX® 10 devices to monitor voltage inputs, you can increase the number of streaming interfaces. To allow external interconnect, export the interfaces from the system.
Power Good Inputs

Specify the number of power good inputs to monitor.

The number must match the value you specify in the other components of the system. Otherwise, the interface bus widths between components will not match.

Component’s Clock Frequency

Read-only parameter that specifies the component's input clock frequency.

  • The number depends on which clock you connect to the component in the Platform Designer.
  • Ensure that this frequency is correct. Otherwise, the system cannot derive the correct debounce values.
Power Good Debounce Setting Select the number of clock cycles (2n) that the power good input signal must be stable before the component forwards the signal downstream.
Power Good Debounce Interval

Calculated parameter that specifies the duration (in µs) for which the power good input must be stable

  • The number is based on the Power Good Debounce Setting that you select.
  • The parameter editor cannot calculate this value if the input clock is not connected to a clock signal or if the rate is unknown.
ADC Interface/PG for VIN

Select the interface that transmits the voltage level to the VIN rail:

  • PG_Input—use a power good signal from the VRAIL_PWRGD[] input bus to control the VIN rail.
  • 1 to 16—the Avalon® -ST ADC interface that transmits the voltage level. The available interface numbers depend on the number of ADC Streaming Interfaces you select.
ADC/PG Channel for VIN

Specify the physical ADC channel (ADC0 to ADC8) or power good input bit to map to the VIN rail.

Table 2.   Sequencer ADC Decoder Parameters - ADC Channel Mapping
Parameter Description
ADC Interface Number/PG

Select the interface that transmits the voltage level to the VOUT rail:

  • PG_Input—use a power good signal from the VRAIL_PWRGD[] input bus to control the VOUT rail.
  • 1 to 16—the Avalon® -ST ADC interface that transmits the voltage level. The available interface numbers depend on the number of ADC Streaming Interfaces you select.
ADC/PG Channel Specify the physical ADC channel (ADC0 to ADC8) or power good input bit to map to the VOUT rail.
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