AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

ID 683778
Date 9/30/2019
Public
Document Table of Contents

2.3.6.1. pll_lock_splitter (PLL_LockSplit)

The pll_lock_splitter component receives the pll_locked signal from the phase-locked loop (PLL), and fans the signal out to the reset logic and the adc_pll_locked input of the Modular ADC Core IP. The Multi-Rail Power Sequencer and Monitor design holds all blocks within it in reset until the PLL locks and becomes stable.

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