AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

ID 683778
Date 3/15/2024
Public
Document Table of Contents

2.3.7.3. pll_lock_splitter (PLL_LockSplit)

The pll_lock_splitter component receives the pll_locked signal from the phaselocked loop (PLL), and fans the signal out to the reset sequencer and the adc_pll_locked input of the Modular ADC Core IP. The Multi-Rail Power Sequencer and Monitor design holds all blocks within it in reset until after the PLL locks and becomes stable.