AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

ID 683778
Date 9/30/2019
Public
Document Table of Contents

5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design

These block diagrams show how to connect Intel® MAX® 10 devices programmed with the reference design on the PCB.
Figure 21. PCB Connection for Intel® MAX® 10 Power Sequencer with Power Good (POK or PG)


Figure 22. PCB Connection for Intel® MAX® 10 Power Sequencer with Voltage Monitoring


Figure 23. PCB Connection for Intel® MAX® 10 Power Sequencer with Fast Discharge FET Circuit


Figure 24. PCB Connection for Intel® MAX® 10 Power Sequencer with Sequence Groups
  • One EN signal per group fans out to multiple regulators.
  • A separate POK signal or voltage monitor feedback is used per rail.
  • You can tie multiple POK signals together for a single input (not shown in this figure).


Figure 25. PCB Connection for Intel® MAX® 10 Power Sequencer with VIN Monitoring and Enable
  • Option to monitor VIN_FAULT or VIN_MON.
  • The sequencer uses only one input or the other.
  • Whichever input the sequencer uses determines if the input rail is within specification.


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