AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

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ID 683778
Date 9/30/2019
Public
Document Table of Contents
Document Table of Contents
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design 2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design 3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design 4. Functionality Level and Resource Utilization Estimates 5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design 6. Document Revision History for AN 896: Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design
1.1. Features of the Reference Design 1.2. Structure of the Reference Design Archive
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design
2.1. Reference Design Architecture 2.2. Reference Design Component Blocks 2.3. Design Components and Parameter Options 2.4. Output Voltage Data Formats and Related Parameters
2.3. Design Components and Parameter Options
2.3.1. Modular ADC Core Intel® FPGA IP (ADC_Core) 2.3.2. Sequencer ADC Decoder (ADC_Decoder) 2.3.3. Sequencer Voltage Monitor (Sequencer_VMonitor) 2.3.4. PMBus* Slave to Avalon®-MM Master Bridge (PMBus_Slave) 2.3.5. Power Sequencer (Sequencer_Core) 2.3.6. Other Design Components
2.3.2. Sequencer ADC Decoder (ADC_Decoder)
2.3.2.1. Sequencer ADC Decoder Parameter Settings
2.3.3. Sequencer Voltage Monitor (Sequencer_VMonitor)
2.3.3.1. Sequencer Voltage Monitor Parameter Settings
2.3.5. Power Sequencer (Sequencer_Core)
2.3.5.1. Power Sequencer Parameter Settings
2.3.6. Other Design Components
2.3.6.1. pll_lock_splitter (PLL_LockSplit) 2.3.6.2. Avalon®-MM Sequencer (AVMM_Initializer)
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design
3.1. Customizing and Generating the Design Example 3.2. Updating the Schematic After Customizing the Design 3.3. Assigning Pins and Compiling the Design Example 3.4. Testbench Simulation to Understand Design Behavior
3.3. Assigning Pins and Compiling the Design Example
3.3.1. Pin Description
3.4. Testbench Simulation to Understand Design Behavior
3.4.1. Generating the Testbench Simulation 3.4.2. Running the Testbench Simulation
4. Functionality Level and Resource Utilization Estimates
4.1. PMBus* Commands Implementation 4.2. Resource Utilization of the Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design
4. Functionality Level and Resource Utilization Estimates
5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design
6. Document Revision History for AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design

These block diagrams show how to connect Intel® MAX® 10 devices programmed with the reference design on the PCB.
Figure 21. PCB Connection for Intel® MAX® 10 Power Sequencer with Power Good (POK or PG)


Figure 22. PCB Connection for Intel® MAX® 10 Power Sequencer with Voltage Monitoring


Figure 23. PCB Connection for Intel® MAX® 10 Power Sequencer with Fast Discharge FET Circuit


Figure 24. PCB Connection for Intel® MAX® 10 Power Sequencer with Sequence Groups
  • One EN signal per group fans out to multiple regulators.
  • A separate POK signal or voltage monitor feedback is used per rail.
  • You can tie multiple POK signals together for a single input (not shown in this figure).


Figure 25. PCB Connection for Intel® MAX® 10 Power Sequencer with VIN Monitoring and Enable
  • Option to monitor VIN_FAULT or VIN_MON.
  • The sequencer uses only one input or the other.
  • Whichever input the sequencer uses determines if the input rail is within specification.


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