AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

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ID 683778
Date 9/30/2019
Public
Document Table of Contents
Document Table of Contents
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design 2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design 3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design 4. Functionality Level and Resource Utilization Estimates 5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design 6. Document Revision History for AN 896: Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design
1.1. Features of the Reference Design 1.2. Structure of the Reference Design Archive
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design
2.1. Reference Design Architecture 2.2. Reference Design Component Blocks 2.3. Design Components and Parameter Options 2.4. Output Voltage Data Formats and Related Parameters
2.3. Design Components and Parameter Options
2.3.1. Modular ADC Core Intel® FPGA IP (ADC_Core) 2.3.2. Sequencer ADC Decoder (ADC_Decoder) 2.3.3. Sequencer Voltage Monitor (Sequencer_VMonitor) 2.3.4. PMBus* Slave to Avalon®-MM Master Bridge (PMBus_Slave) 2.3.5. Power Sequencer (Sequencer_Core) 2.3.6. Other Design Components
2.3.2. Sequencer ADC Decoder (ADC_Decoder)
2.3.2.1. Sequencer ADC Decoder Parameter Settings
2.3.3. Sequencer Voltage Monitor (Sequencer_VMonitor)
2.3.3.1. Sequencer Voltage Monitor Parameter Settings
2.3.5. Power Sequencer (Sequencer_Core)
2.3.5.1. Power Sequencer Parameter Settings
2.3.6. Other Design Components
2.3.6.1. pll_lock_splitter (PLL_LockSplit) 2.3.6.2. Avalon®-MM Sequencer (AVMM_Initializer)
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design
3.1. Customizing and Generating the Design Example 3.2. Updating the Schematic After Customizing the Design 3.3. Assigning Pins and Compiling the Design Example 3.4. Testbench Simulation to Understand Design Behavior
3.3. Assigning Pins and Compiling the Design Example
3.3.1. Pin Description
3.4. Testbench Simulation to Understand Design Behavior
Important Caveats for the Simulation 3.4.1. Generating the Testbench Simulation 3.4.2. Running the Testbench Simulation
4. Functionality Level and Resource Utilization Estimates
4.1. PMBus* Commands Implementation 4.2. Resource Utilization of the Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design
4. Functionality Level and Resource Utilization Estimates
5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design
6. Document Revision History for AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

3.4. Testbench Simulation to Understand Design Behavior

The Multi-Rail Power Sequencer and Monitor reference design includes a simple testbench that you can use as a springboard to understand design behavior. The testbench implements a six-rail voltage-monitored sequencer design with full functionality.

Important Caveats for the Simulation

  • The analog inputs for the ADC come from voltage levels listed in text files. The simulation continuosly loops through these text files. Therefore, the VRAIL_EN signal has no effect on the simulated analog input.
  • The analog input does not rise or fall when VRAIL_EN asserts and deasserts. If you modify the simulation behavior, create simulation voltage files—adcsim_ch#.txt files—that match the intent of the simulation test.
  • If you configure the design to use external POWER_GOOD signals for simulation, you must incorporate a design block—as simple as a loopback—that adjusts the POWER_GOOD status based on the VRAIL_EN level.

Section Content
Generating the Testbench Simulation
Running the Testbench Simulation

Level Two Title

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