AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

ID 683778
Date 9/30/2019
Public
Document Table of Contents

3.4. Testbench Simulation to Understand Design Behavior

The Multi-Rail Power Sequencer and Monitor reference design includes a simple testbench that you can use as a springboard to understand design behavior. The testbench implements a six-rail voltage-monitored sequencer design with full functionality.

Important Caveats for the Simulation

  • The analog inputs for the ADC come from voltage levels listed in text files. The simulation continuosly loops through these text files. Therefore, the VRAIL_EN signal has no effect on the simulated analog input.
  • The analog input does not rise or fall when VRAIL_EN asserts and deasserts. If you modify the simulation behavior, create simulation voltage files—adcsim_ch#.txt files—that match the intent of the simulation test.
  • If you configure the design to use external POWER_GOOD signals for simulation, you must incorporate a design block—as simple as a loopback—that adjusts the POWER_GOOD status based on the VRAIL_EN level.

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