AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

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ID 683778
Date 9/30/2019
Public
Document Table of Contents
Document Table of Contents
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design 2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design 3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design 4. Functionality Level and Resource Utilization Estimates 5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design 6. Document Revision History for AN 896: Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design
1.1. Features of the Reference Design 1.2. Structure of the Reference Design Archive
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design
2.1. Reference Design Architecture 2.2. Reference Design Component Blocks 2.3. Design Components and Parameter Options 2.4. Output Voltage Data Formats and Related Parameters
2.3. Design Components and Parameter Options
2.3.1. Modular ADC Core Intel® FPGA IP (ADC_Core) 2.3.2. Sequencer ADC Decoder (ADC_Decoder) 2.3.3. Sequencer Voltage Monitor (Sequencer_VMonitor) 2.3.4. PMBus* Slave to Avalon®-MM Master Bridge (PMBus_Slave) 2.3.5. Power Sequencer (Sequencer_Core) 2.3.6. Other Design Components
2.3.2. Sequencer ADC Decoder (ADC_Decoder)
2.3.2.1. Sequencer ADC Decoder Parameter Settings
2.3.3. Sequencer Voltage Monitor (Sequencer_VMonitor)
2.3.3.1. Sequencer Voltage Monitor Parameter Settings
2.3.5. Power Sequencer (Sequencer_Core)
2.3.5.1. Power Sequencer Parameter Settings
2.3.6. Other Design Components
2.3.6.1. pll_lock_splitter (PLL_LockSplit) 2.3.6.2. Avalon®-MM Sequencer (AVMM_Initializer)
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design
3.1. Customizing and Generating the Design Example 3.2. Updating the Schematic After Customizing the Design 3.3. Assigning Pins and Compiling the Design Example 3.4. Testbench Simulation to Understand Design Behavior
3.3. Assigning Pins and Compiling the Design Example
3.3.1. Pin Description
3.4. Testbench Simulation to Understand Design Behavior
3.4.1. Generating the Testbench Simulation 3.4.2. Running the Testbench Simulation
4. Functionality Level and Resource Utilization Estimates
4.1. PMBus* Commands Implementation 4.2. Resource Utilization of the Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design
4. Functionality Level and Resource Utilization Estimates
5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design
6. Document Revision History for AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

2.3.4. PMBus* Slave to Avalon®-MM Master Bridge (PMBus_Slave)

The PMBus* Slave to Avalon®-MM Master Bridge component is optional. You can remove the component from the design if you do not need it.

If you enable the PMBus* interface, each power rail that is monitored by one of the ADC VIN pins are on its own page:

  • The page numbers of the VOUT rails are sequential and start from zero. For example, in a six-rail sequencer with rails VOUT0 through VOUT5, page zero shows rail zero (VOUT0), page one shows rail one (VOUT1), and so forth.
  • The registers associated with VIN are visible across all pages. If you clear an input fault on one page, the design clears the fault on all pages.

The PMBus* interface does not support a page setting of 0xFF (broadcasting commands to all pages). The interface only allows for pages that correspond to a monitored VIN rail (page zero), or monitored VOUT rails.

  • If an ADC pin does not monitor a rail—the rail uses an external power good signal such as the POK signal from the regulator—the page for the rail is invalid. Any attempt to change to that page causes a PMBus* error bit 6 (Invalid or unsupported data received) report to the STATUS_CML register.
  • If your system monitors only the VIN rail while all VOUT rails use external power good indicators, VIN exists on page zero. All VOUT-related commands result in a PMBus* error bit 7 (Invalid or unsupported command received) report to the STATUS_CML register.
  • If your system does not monitor the VIN rail, all VIN-related commands result in a PMBus* error bit 7 (Invalid or unsupported command received) report the STATUS_CML register.
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