AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

ID 683778
Date 9/30/2019
Public
Document Table of Contents

2.3.4. PMBus* Slave to Avalon®-MM Master Bridge (PMBus_Slave)

The PMBus* Slave to Avalon®-MM Master Bridge component is optional. You can remove the component from the design if you do not need it.

If you enable the PMBus* interface, each power rail that is monitored by one of the ADC VIN pins are on its own page:

  • The page numbers of the VOUT rails are sequential and start from zero. For example, in a six-rail sequencer with rails VOUT0 through VOUT5, page zero shows rail zero (VOUT0), page one shows rail one (VOUT1), and so forth.
  • The registers associated with VIN are visible across all pages. If you clear an input fault on one page, the design clears the fault on all pages.

The PMBus* interface does not support a page setting of 0xFF (broadcasting commands to all pages). The interface only allows for pages that correspond to a monitored VIN rail (page zero), or monitored VOUT rails.

  • If an ADC pin does not monitor a rail—the rail uses an external power good signal such as the POK signal from the regulator—the page for the rail is invalid. Any attempt to change to that page causes a PMBus* error bit 6 (Invalid or unsupported data received) report to the STATUS_CML register.
  • If your system monitors only the VIN rail while all VOUT rails use external power good indicators, VIN exists on page zero. All VOUT-related commands result in a PMBus* error bit 7 (Invalid or unsupported command received) report to the STATUS_CML register.
  • If your system does not monitor the VIN rail, all VIN-related commands result in a PMBus* error bit 7 (Invalid or unsupported command received) report the STATUS_CML register.

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