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1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design
4. Functionality Level and Resource Utilization Estimates
5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design
6. Document Revision History for AN 896: Multi-Rail Power Sequencer and Monitor Reference Design
2.3.1. Reset Sequencer (Reset_Sequencer)
2.3.2. Modular ADC Core Intel® FPGA IP (ADC_Core)
2.3.3. Sequencer Monitor (Sequencer_Monitor)
2.3.4. PMBus* Slave to Avalon®-MM Master Bridge (PMBus_Slave)
2.3.5. Power Sequencer (Sequencer_Core)
2.3.6. MAX10 OCFlash Controller (NVRAM_Controller)
2.3.7. On-Chip Flash Intel® FPGA IP (NVRAM_OC_Flash)
2.3.8. Other Design Components
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2.3.4. PMBus* Slave to Avalon®-MM Master Bridge (PMBus_Slave)
The PMBus* Slave to Avalon®-MM Master Bridge component is optional. You can remove the component from the design if you do not need it.
If you enable the Sequencer Monitor's control interface (via the Functionality Level parameter), each power rail has its own page:
- The page numbers of the VOUT rails are sequential and start from zero. For example, in a six-rail sequencer with rails VOUT0 through VOUT5, page zero shows rail zero (VOUT0), page one shows rail one (VOUT1), and so forth.
- The registers associated with VIN are visible across all pages. If you clear an input fault on one page, the design clears the fault on all pages.
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The PMBus* interface does not support a page setting of 0xFF (broadcasting commands to all pages). The interface only allows for pages that correspond to valid VIN and VOUT rails.
- If an ADC pin does not monitor a rail—the rail uses an external power good signal such as the POK signal from the regulator—certain PMBus* commands are not supported. Invalid command accesses result in a PMBus* error bit 7 (Invalid or unsupported command received) report to the STATUS_CML register.