AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

ID 683778
Date 9/30/2019
Public
Document Table of Contents

2.3.3. Sequencer Voltage Monitor (Sequencer_VMonitor)

The Sequencer Voltage Monitor component performs two primary functions:

  • Monitors the voltage levels provided by the ADC inputs, providing status and alerts via PMBus* communication
  • Creates internal power good status levels (POK signals) that the Power Sequencer component uses to appropriately power up and down the various VOUT rails.

You can configure several parameters for the Sequencer Voltage Monitor component. For a proper interface to the Sequencer ADC Decoder component, you must accurately specify the number of Output Voltage Rails and Power Good Inputs parameters.

Figure 8.  Sequencer Voltage Monitor Parameter Editor


To prevent false errors or warnings that may be caused by noise on monitored voltage rails, specify the ADC Samples to Check parameter. The design only reports an error or warning condition if the condition is present for the number of samples you specify in this parameter.

The interval duration depends on the sample rate and sequencer configuration in the ADC. For example, assume that you configure the Modular ADC Core IP sequencer to process the inputs in a round-robin fashion, reporting the voltage levels for each channel in sequence over seven time slots. If the sample rate is 1 MSPS and you configure the Sequencer Voltage Monitor component to check that five samples exceed the threshold before declaring a warning or error, then the warning or error must be present for .

Note: The Retry Attempts and Timeout Interval on Retry parameters are global settings. You can dynamically control these settings through the subset of PMBus* commands that affect any of the VIN or VOUT error responses. Changing the response behavior of one command affects all commands that have these parameters.

If an ADC VIN pin monitors a rail, either one of these settings determines the rail’s power good status:

  • The levels set in the default configuration of the Sequencer Voltage Monitor within the Platform Designer.
  • The dynamically modified levels set through the PMBus* interface.

The Power Sequencer component uses the power good status outputs to sequence the power regulators on or off.

The following PMBus* commands dynamically adjust the levels to assert or deassert the internal power good signal:

  • VIN_ON and VIN_OFF commands dynamically adjust the levels at which the internal power good status is asserted or removed for VIN.
  • POWER_GOOD_ON and POWER_GOOD_OFF commands dynamically adjust the levels at which the internal power good status is asserted or removed for VOUT.

The following thresholds provide you with a comprehensive monitoring approach to safely track all input and output voltages and allow you to automatically or manually sequence a power down of the rails in case of an error:

  • Undervoltage warning
  • Undervoltage fault
  • Overvoltage warning
  • Overvoltage fault
Figure 9. Voltage ThresholdsIn this figure, as the rail's voltage ramps up, the voltage can pass through one of the six possible voltage thresholds.


After the system enables the voltage rail and its level rises, the rail transitions through the undervoltage fault region and into the power good region. While power good is not asserted, the design masks all voltage faults for a given rail so that this portion of the ramp up cycle is not marked as a fault.

After the system reaches the power good level, the rail is still in a state that causes undervoltage warning reports. This behavior is normal and expected. The PMBus may report undervoltage warnings for some of the rails depending on ADC sample rates and the rise time of the rail.

Once the rail reaches its nominal voltage, send the CLEAR_FAULTS command to clear out any latched warnings in the VOUT status registers. You can safely ignore these latched warnings. At this point, the system should be in a normal operation state.

If the rail drifts outside the typical operating range for longer than the duration set in the ADC Samples to Check parameter, the design reports overvoltage or undervoltage warnings. The warning causes assertion of the SMB_ALERTN pin. If no other devices are asserting SMB_ALERTN at this time, the page associated with the warning also asserts STATUS_OTHER bit 0: First to Assert SMBALERT#. You can use this status to indicate which rail was the first to experience an error. If the rail exceeds the levels for an overvoltage or undervoltage fault for longer than the duration specified in the ADC Samples to Check parameter, the system behaves according to the programmed response.

In the Sequencer Voltage Monitor component, there are independent checkboxes for each rail. These independent settings allow you to specify a controlled automatic power down sequence in case of overvoltage or undervoltage faults. You can adjust these responses dynamically with the PMBus* commands VIN_OV_FAULT_RESP, VIN_UV_FAULT_RESP, VOUT_OV_FAULT_RESP, and VOUT_UV_FAULT_RESP.

The sequencer supports four different behaviors for a fault:

  • Ignore that fault and continue operation
  • Sequence an immediate power down
  • Retry for a selectable number of times from one to six attempts
  • Retry indefinitely

The Power Sequencer component does not retry power sequencing until all power good signals for the VOUT rails are deasserted. To specify the duration between retry attempts, set the Delay Time Between Restarts parameter in the Power Sequencer component parameter editor. The timer starts after the power good signals deassert.

If a rail uses an external power good signal—typically, a POK output from a power supply—and the ADC VIN does not monitor the rail, the design passes the external power good signal directly to the sequencer. In this case, you cannot perform any PMBus* -accessible monitoring or adjustments for that rail.

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