AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

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ID 683778
Date 3/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design 2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design 3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design 4. Functionality Level and Resource Utilization Estimates 5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design 6. Document Revision History for the AN 896: Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design x
1.1. Features of the Reference Design 1.2. Structure of the Reference Design Archive
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design x
2.1. Reference Design Architecture 2.2. Reference Design Component Blocks 2.3. Design Components and Parameter Options 2.4. Output Voltage Data Formats and Related Parameters
2.3. Design Components and Parameter Options x
2.3.1. Reset Sequencer (Reset_Sequencer) 2.3.2. Modular ADC Core Intel® FPGA IP (ADC_Core) 2.3.3. Sequencer ADC Decoder (ADC_Decoder) 2.3.4. Sequencer Voltage Monitor (Sequencer_VMonitor) 2.3.5. PMBus* Slave to Avalon®-MM Master Bridge (PMBus_Slave) 2.3.6. Power Sequencer (Sequencer_Core) 2.3.7. Other Design Components
2.3.3. Sequencer ADC Decoder (ADC_Decoder) x
2.3.3.1. Sequencer ADC Decoder Parameter Settings
2.3.4. Sequencer Voltage Monitor (Sequencer_VMonitor) x
2.3.4.1. Sequencer Voltage Monitor Parameter Settings
2.3.6. Power Sequencer (Sequencer_Core) x
2.3.6.1. Power Sequencer Parameter Settings
2.3.7. Other Design Components x
2.3.7.1. POR Pulse (POR_Pulse) 2.3.7.2. Reset to Conduit Adapter (Reset2Conduit) 2.3.7.3. pll_lock_splitter (PLL_LockSplit) 2.3.7.4. Avalon®-MM Sequencer (AVMM_Initializer)
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design x
3.1. Customizing and Generating the Design Example 3.2. Updating the Schematic After Customizing the Design 3.3. Assigning Pins and Compiling the Design Example 3.4. Testbench Simulation to Understand Design Behavior
3.3. Assigning Pins and Compiling the Design Example x
3.3.1. Pin Description
3.4. Testbench Simulation to Understand Design Behavior x
3.4.1. Generating the Testbench Simulation 3.4.2. Running the Testbench Simulation
4. Functionality Level and Resource Utilization Estimates x
4.1. PMBus* Commands Implementation 4.2. Resource Utilization of the Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design
4. Functionality Level and Resource Utilization Estimates
5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design
6. Document Revision History for the AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

3.1. Customizing and Generating the Design Example

  1. From the Quartus® Prime main menu, click File > Open Project.
  2. Select the <installation directory>\quartus\Sequencer.qpf file and click Open.
    Note: Ignore the warning message about the missing sequencer_qsys.qip file. The Platform Designer will generate this file when you generate the system later.
  3. From the Quartus® Prime main menu, click File > Open.
  4. Select the <installation directory>\source\sequencer_qsys.qsys file and click Open.
    Note: Do not select the sequencer_qsys_tb.qsys file, which is the simulation testbench system.
    The Platform Designer opens with the reference design system.
  5. Customize the parameters of the components according to your system requirements.
    Many of the components have built-in error checks to prevent you from generating invalid code. Check the Messages pane for interface mismatches between components or potentially incorrect settings.
  6. The example project defines the reference clock frequency as 50 MHz. If this frequency changes, edit the ALTPLL IP (PLL_Main) to specify the new reference clock frequency in the What is the frequency of the inclk0 input? box.
    Figure 13. PLL_Main Parameter Editor in the Platform Designer


  7. After you have completed all customizations, click Generate HDL in the Platform Designer window.
  8. In the Generation window:
    1. Select Verilog or VHDL in the Create HDL design files for synthesis box.
    2. Turn on Create block symbol file (.bsf).
    3. Click Generate.
    Figure 14.  Platform Designer Generation Window


  9. In the Generate Completed window, click Close.

If you make any changes to the design after generating the sequencer code, you must update the top-level schematic to match the customizations.

Note:

The Platform Designer regenerates the following files automatically with the parameter settings you specify. Ensure that these files in the source directory are writable. Do not place them under version control. If these files are not writable, the generated design cannot parameterize them accurately:

  • sequencer_params_pkg.sv
  • sequencer_vmon_pkg.sv
  • sequencer_vmondecode_pkg.sv
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