AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

ID 683778
Date 3/15/2024
Document Table of Contents

3.1. Customizing and Generating the Design Example

  1. From the Quartus® Prime main menu, click File > Open Project.
  2. Select the <installation directory>\quartus\Sequencer.qpf file and click Open.
    Note: Ignore the warning message about the missing sequencer_qsys.qip file. The Platform Designer will generate this file when you generate the system later.
  3. From the Quartus® Prime main menu, click File > Open.
  4. Select the <installation directory>\source\sequencer_qsys.qsys file and click Open.
    Note: Do not select the sequencer_qsys_tb.qsys file, which is the simulation testbench system.
    The Platform Designer opens with the reference design system.
  5. Customize the parameters of the components according to your system requirements.
    Many of the components have built-in error checks to prevent you from generating invalid code. Check the Messages pane for interface mismatches between components or potentially incorrect settings.
  6. The example project defines the reference clock frequency as 50 MHz. If this frequency changes, edit the ALTPLL IP (PLL_Main) to specify the new reference clock frequency in the What is the frequency of the inclk0 input? box.
    Figure 13. PLL_Main Parameter Editor in the Platform Designer

  7. After you have completed all customizations, click Generate HDL in the Platform Designer window.
  8. In the Generation window:
    1. Select Verilog or VHDL in the Create HDL design files for synthesis box.
    2. Turn on Create block symbol file (.bsf).
    3. Click Generate.
    Figure 14.  Platform Designer Generation Window

  9. In the Generate Completed window, click Close.

If you make any changes to the design after generating the sequencer code, you must update the top-level schematic to match the customizations.


The Platform Designer regenerates the following files automatically with the parameter settings you specify. Ensure that these files in the source directory are writable. Do not place them under version control. If these files are not writable, the generated design cannot parameterize them accurately: