1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design 2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design 3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design 4. Functionality Level and Resource Utilization Estimates 5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design 6. Document Revision History for AN 896: Multi-Rail Power Sequencer and Monitor Reference Design
3.2. Updating the Schematic After Customizing the Design
After sequencer code generation, if you make changes that affect the top level design, you must update the top-level schematic accordingly to match the customizations.
- If you remove the PMBus* Slave to Avalon®-MM Master Bridge component, you must remove the SMB_SCL and SMB_SDA signals too.
- If you increase or decrease the number of rails, you must change the widths of the VRAIL_POK, VRAIL_ENA, and VRAIL_DCHG signals accordingly.
Figure 14. Updating Symbol in Top-Level Schematic of the Sequencer Component
- In the Project Navigator, double click the sequencer block diagram file to open it in the Block Editor window.
- In the sequencer schematic, right-click on the sequencer_qsys block and select Update Symbol or Block.
The sequencer_qsys block updates. For example, the update removes the PMBus* ports and decreases the bus widths of the vrail_ena and vrail_dchg ports from six bits to four bits.
- Edit the connections from the I/O signals to the sequencer_qsys block.
For example, remove the SMB_SCL and SMB_SDA signals that are not used anymore. Then, edit the bus widths of the VRAIL_ENA and VRAIL_DCHG signals and reconnect them back to the vrail_ena and vrail_dchg ports.Figure 15. Correcting the I/O Connections in the Top Level Schematic
- Save the sequencer schematic and close the Block Editor window.
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