AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

ID 683778
Date 3/15/2024
Document Table of Contents

2.3.1. Reset Sequencer (Reset_Sequencer)

This block provides a controlled reset sequence to the power sequencer design. After configuration and upon entering user mode, a programmable reset pulse is generated by POR_Pulse to the Reset_Sequencer. The Reset_Sequencer re-synchronizes the pulse and asserts reset_out0 (refer to the following figure at time interval 1), which is used to reset the PLL. It waits for the PLL to lock, debouncing it for 128 clock cycles (refer to the following figure at time interval 2) after which it asserts the system reset.

Figure 5. Reset Sequencer