AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

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ID 683778
Date 4/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design 2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design 3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design 4. Functionality Level and Resource Utilization Estimates 5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design 6. Document Revision History for AN 896: Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design x
1.1. Features of the Reference Design 1.2. Structure of the Reference Design Archive
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design x
2.1. Reference Design Architecture 2.2. Reference Design Component Blocks 2.3. Design Components and Parameter Options 2.4. Output Voltage Data Formats and Related Parameters
2.3. Design Components and Parameter Options x
2.3.1. Reset Sequencer (Reset_Sequencer) 2.3.2. Modular ADC Core Intel® FPGA IP (ADC_Core) 2.3.3. Sequencer Monitor (Sequencer_Monitor) 2.3.4. PMBus* Slave to Avalon®-MM Master Bridge (PMBus_Slave) 2.3.5. Power Sequencer (Sequencer_Core) 2.3.6. MAX10 OCFlash Controller (NVRAM_Controller) 2.3.7. On-Chip Flash Intel® FPGA IP (NVRAM_OC_Flash) 2.3.8. Other Design Components
2.3.3. Sequencer Monitor (Sequencer_Monitor) x
2.3.3.1. Sequencer Monitor Parameter Settings
2.3.5. Power Sequencer (Sequencer_Core) x
2.3.5.1. Power Sequencer Parameter Settings
2.3.6. MAX10 OCFlash Controller (NVRAM_Controller) x
2.3.6.1. MAX10 OCFlash Controller Parameter Settings
2.3.8. Other Design Components x
2.3.8.1. POR Pulse (POR_Pulse) 2.3.8.2. Reset to Conduit Adapter (Reset2Conduit) 2.3.8.3. pll_lock_splitter (PLL_LockSplit) 2.3.8.4. Avalon®-MM Sequencer (AVMM_Initializer) 2.3.8.5. Alignment Bridge (PM2AVMM_Align)
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design x
3.1. Customizing and Generating the Design Example 3.2. Updating the Schematic After Customizing the Design 3.3. Assigning Pins and Compiling the Design Example 3.4. Testbench Simulation to Understand Design Behavior 3.5. Controlling the Sequencer using System Console
3.3. Assigning Pins and Compiling the Design Example x
3.3.1. Pin Description
3.4. Testbench Simulation to Understand Design Behavior x
3.4.1. Generating the Testbench Simulation 3.4.2. Running the Testbench Simulation
3.5. Controlling the Sequencer using System Console x
3.5.1. Interacting with the Sequencer through System Console
4. Functionality Level and Resource Utilization Estimates x
4.1. PMBus* Commands Implementation 4.2. PMBus* STATUS Command Descriptions 4.3. Resource Utilization of the Multi-Rail Power Sequencer and Monitor Reference Design
4.2. PMBus* STATUS Command Descriptions x
4.2.1. STATUS_BYTE Command Description 4.2.2. STATUS_WORD Command Description 4.2.3. STATUS_VOUT Command Description 4.2.4. STATUS_INPUT Command Description 4.2.5. STATUS_CML Command Description 4.2.6. STATUS_OTHER Command Description
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design
4. Functionality Level and Resource Utilization Estimates
5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design
6. Document Revision History for AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

6. Document Revision History for AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

Document Version Changes
2024.04.24
  • Updated Features of the Reference Design in the Overview of the Reference Design chapter.
  • Added a NV error log block to the following figures:
    • Figure: Multi-Rail Power Sequencer and Monitor Top Level Block Diagram
    • Figure: Multi-Rail Power Sequencer and Monitor Design Blocks
  • Updated the Architecture and Operation of the Reference Design chapter:
    • Updated mentions of Sequencer Voltage Monitor to Sequencer Monitor throughout the document.
    • Updated Figure: Full-featured Multi-Rail Power Sequencer and Monitor Implementation in the Platform Designer .
    • Updated Modular ADC Core Intel® FPGA IP (ADC_Core).
    • Removed the following sections:
      • Sequencer ADC Decoder (ADC_Decoder)
      • Sequencer Voltage Monitor (Sequencer_VMonitor)
    • Added new sections:
      • Sequencer Monitor (Sequencer_Monitor)
      • MAX10 OCFlash Controller (NVRAM_Controller)
      • On-Chip Flash Intel® FPGA IP (NVRAM_OC_Flash)
    • Added a new topic to the Other Design Components section—Alignment Bridge (PM2AVMM_Align).
  • Updated the Implementation and Simulation of the Reference Design chapter:
    • Added a new section—Controlling the Sequencer using System Console.
  • Updated the Functionality Level and Resource Utilization Estimates chapter:
    • Updated Table: Power Sequencer PMBus* Commands Description in PMBus* Commands Implementation.
    • Added new section— PMBus* STATUS Command Descriptions.
    • Added a note to Resource Utilization of the Reference Design.
    • Updated Table: Approximate Resource Estimate for MAX® 10 Device.
2024.03.15
  • Added Reset Sequencer (Reset_Sequencer) section.
  • Updated Power Sequencer Parameter Editor figure in Power Sequencer (Sequencer_Core).
  • Added POR Pulse (POR_Pulse) section.
  • Added Reset to Conduit Adapter (Reset2Conduit) section.
  • Updated pll_lock_splitter (PLL_LockSplit) section.
  • Updated Power Sequencer Signals table in Pin Description section.
  • Updated Multi-Rail Power Sequencer and Monitor Testbench Simulation Waveforms figure in Running the Testbench Simulation section.
  • Updated instances of Intel® Enpirion® PowerSoC to DC Regulator.
2019.09.30 Initial release.
Level Two Title