AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

ID 683778
Date 9/30/2019
Public
Document Table of Contents

2.1. Reference Design Architecture

Figure 2.  Multi-Rail Power Sequencer and Monitor Top Level Block Diagram


The reference design passes the remapped and decoded inputs to the Sequencer Voltage Monitor component. The Sequencer Voltage Monitor component checks and reports the statuses, among others, for the power good signal, undervoltage, overvoltage, alarms, and present voltage levels.

The reference design provides information about the state of the various rails to the PMBus* slave interface, a protocol that operates on the I2C physical interface. The design is compliant to the PMBus* 1.3.1 specification and can operate in 100 KHz and 400 KHz modes.

The Power Sequencer component implements a sequential approach when powering up the rails and powers them down in the reverse order. The Power Sequencer component uses the output of the Sequencer Voltage Monitor component to enable and disable the various power rails.

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