AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

ID 683778
Date 9/30/2019
Public
Document Table of Contents

4.2. Resource Utilization of the Multi-Rail Power Sequencer and Monitor Reference Design

Table 10.  Approximate Resource Estimate for Intel® MAX® 10 Device
Configuration Component Logic Elements Flip-Flops
Six-rail sequencer with all rails monitored and full PMBus* support Modular ADC Core 120 90
Sequencer ADC Decoder 300 100
Sequencer Voltage Monitor 2125 1000
PMBus* Slave to Avalon®-MM Master Bridge 150 100
Power Sequencer 175 80
Total Resources 2870 1370
Six-rail sequencer with all rails monitored and hardcoded PMBus* thresholds Modular ADC Core 120 90
Sequencer ADC Decoder 300 100
Sequencer Voltage Monitor 1025 500
PMBus* Slave to Avalon®-MM Master Bridge 150 100
Power Sequencer 175 80
Total Resources 1770 870
Six-rail sequencer with all rails monitored but no PMBus* support Modular ADC Core 120 90
Sequencer ADC Decoder 300 100
Sequencer Voltage Monitor 225 130
Power Sequencer 175 80
Total Resources 820 400
Three-rail sequencer with all rails monitored and full PMBus* support Modular ADC Core 120 90
Sequencer ADC Decoder 200 60
Sequencer Voltage Monitor 1300 575
PMBus* Slave to Avalon®-MM Master Bridge 150 100
Power Sequencer 120 60
Total Resources 1870 885
Six-rail sequencer with no rails monitored and no PMBus* support Power Sequencer 160 80
Total Resources 160 80

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