Specify the number of output voltage rails to sequence.

The number must match the value you specify in the other components of the system. Otherwise, the interface bus widths between components will not match.

Specify the number of power good inputs to monitor.

The number must match the value you specify in the other components of the system. Otherwise, the interface bus widths between components will not match.

Read-only parameter that specifies the component's input clock frequency.

• The number depends on which clock you connect to the component in the Platform Designer.
• Ensure that this frequency is correct. Otherwise, the system cannot derive the correct debounce values.

Select the number of clock cycles (2ⁿ) that the power good input signal must be stable before the component forwards the signal downstream.

Calculated parameter that specifies the duration (in µs) for which the power good input must be stable.

• The number is based on the Power Good Debounce Setting that you select.
• The parameter editor cannot calculate this value if the input clock is not connected to a clock signal or if the rate is unknown.

Select the number of Avalon® -ST interfaces from the Sequencer ADC Decoder to the Modular ADC Core IP.

• A single-ADC MAX® 10 device has one interface while a dual-ADC MAX 10 device has two Avalon® -ST interfaces.
• If you use several MAX® 10 devices to monitor voltage inputs, you can increase the number of streaming interfaces. To allow external interconnect, export the interfaces from the system.

Specify the reference voltage value.

The component uses this value to calculate the various power good, undervoltage, and overvoltage thresholds to compare to the ADC output.

Specify the number of contiguous ADC samples to check per input before declaring a warning or a fault such as overvoltage, undervoltage, and power good on or off.

Select the functionality level of the Sequencer Monitor component:

• No Control Interface—the design uses the hardcoded levels specified in the parameter editor. Dynamic adjustment or monitoring via the PMBus* is not available.
• Hard-Coded Thresholds—you can use the PMBus* Slave to Avalon®-MM Master Bridge to monitor fault and status but you cannot dynamically adjust the voltage level thresholds.
• Full-featured—the design contains the full PMBus* command set for dynamic adjustment, status, and error monitoring. For more information, refer to the related information.

This option allows you to optimize the design and reduce its overall logic footprint. For the logic utilization estimates, refer to the related information.

Select the error logging level of the Sequencer Monitor component:

• No Logging—the design does not log any errors to flash.
• Error Logging; no Black Box—sequencer errors are logged to flash, but Black Box data (which is the current status for all rails at the time of the error) is not logged, in order to reduce write time to flash.
• Full logging support—sequencer errors are logged to flash, as well as Black Box data (which is the current status for all rails at the time of the error).

This option allows you to optimize the design and reduce its overall logic footprint. For the logic utilization estimates, refer to the related information.

• Logs disabled—upon startup, the register controlled by the MFR_NV_MASTER_EN command defaults to having the global and Black Box logs disabled.
• Error Log enabled; Black Box disabled—upon startup, the register controlled by the MFR_NV_MASTER_EN command defaults to having the global log enabled and Black Box log disabled.
• Error and Black Box Logs enabled—upon startup, the register controlled by the MFR_NV_MASTER_EN command defaults to having the global and Black Box logs enabled.

This option adjusts the default value for the global and Black Box log enables. They can be dynamically adjusted by software access to the MFR_NV_MASTER_EN command.

Specify the number of attempts the Power Sequencer component should make to sequence power up—following a complete, controlled sequence down—after detecting an error condition.

Select the delay interval the Power Sequencer component waits before retrying the power up sequence:

• No Delay—retries the power up sequence immediately after all rails have sequenced down
• Use Delay Specified by the Sequencer—delays the retry attempts according to the Delay Time Between Restarts setting in the Power Sequencer component

Select the interface that transmits the voltage level to the VIN rail:

• PG_Input—use a power good signal from the VRAIL_PWRGD[] input bus to control the VIN rail.
• 1 to 16—the Avalon® -ST ADC interface that transmits the voltage level. The available interface numbers depend on the number of ADC Streaming Interfaces you select.

Specify the physical ADC channel (ADC0 to ADC8) or power good input bit to map to the VIN rail.

Select the interface that transmits the voltage level to the VOUT rail:

• PG_Input—use a power good signal from the VRAIL_PWRGD[] input bus to control the VOUT rail.
• 1 to 16—the Avalon® -ST ADC interface that transmits the voltage level. The available interface numbers depend on the number of ADC Streaming Interfaces you select.

Specify the physical ADC channel (ADC0 to ADC8) or power good input bit to map to the VOUT rail.

Specify the typical voltage level that you expect to observe at the ADC analog input.

In your expectation, include the effect of all voltage divider circuitries on the board.

Specify the percentage of the VIN/VOUTN Typical Voltage, Monitored at which to declare an overvoltage fault.

Specify the percentage of the VIN/VOUTN Typical Voltage, Monitored at which to declare an overvoltage warning.

Specify the percentage of the VIN/VOUTN Typical Voltage, Monitored at which to declare an undervoltage warning.

VIN ON Level

(VIN tab only)

Specify the percentage of the VIN Typical Voltage, Monitored at which to consider the monitored input rail as good and start the power up sequencing of the output rails.

VOUT Power Good Assertion Level

(VOUTN tabs only)

Specify the percentage of the VOUTN Typical Voltage, Monitored at which to consider the output voltage of the rail as good and start the power up sequencing of the next output rail.

Specify the percentage of the VIN/VOUTN Typical Voltage, Monitored at which to declare an undervoltage fault.

VIN OFF Level

(VIN tab only)

Specify the percentage of the VIN Typical Voltage, Monitored at which to consider the monitored input rail as bad and start the power down sequencing of all rails.

VOUTN Power Good Deassertion Level

(VOUTN tabs only)

Specify the percentage of the VOUTN Typical Voltage, Monitored at which to consider the output voltage of the rail as bad and start the power down sequencing of all rails.

Turn this on to sequence power down for all rails, based on the fault response, if the component detects an overvoltage fault in the VIN or VOUTN rail.

Turn this on to sequence power down for all rails, based on the fault response, if the component detects an undervoltage fault in the VIN or VOUTN rail.