Specify the number of output voltage rails to sequence.

The number must match the value you specify in the other components of the system. Otherwise, the interface bus widths between components will not match.

Specify the number of power good inputs to monitor.

The number must match the value you specify in the other components of the system. Otherwise, the interface bus widths between components will not match.

Specify the reference voltage value.

The component uses this value to calculate the various power good, undervoltage, and overvoltage thresholds to compare to the ADC output.

Select the functionality level of the Sequencer Voltage Monitor component:

• No PMBus—the design uses the hardcoded levels specified in the parameter editor. Dynamic adjustment or monitoring via the PMBus* is not available.
• Hard-Coded Thresholds—you can use the PMBus* Slave to Avalon®-MM Master Bridge to monitor fault and status but you cannot dynamically adjust the voltage level thresholds.
• Full-featured—the design contains the full PMBus* command set for dynamic adjustment, status, and error monitoring. For more information, refer to the related information.

This option allows you to optimize the design and reduce its overall logic footprint. For the logic utilization estimates, refer to the related information.

Specify the number of contiguous ADC samples to check per input before declaring a warning or a fault such as overvoltage, undervoltage, and power good on or off.

Specify the number of attempts the Power Sequencer component should make to sequence power up—following a complete, controlled sequence down—after detecting an error condition.

Select the delay interval the Power Sequencer component waits before retrying the power up sequence:

• No Delay—retries the power up sequence immediately after all rails have sequenced down
• Use Delay Specified by the Sequencer—delays the retry attempts according to the Delay Time Between Restarts setting in the Power Sequencer component

Specify the typical voltage level that you expect to observe at the ADC analog input.

In your expectation, include the effect of all voltage divider circuitries on the board.

Specify the percentage of the VIN/VOUTN Typical Voltage, Monitored at which to declare an overvoltage fault.

Specify the percentage of the VIN/VOUTN Typical Voltage, Monitored at which to declare an overvoltage warning.

Specify the percentage of the VIN/VOUTN Typical Voltage, Monitored at which to declare an undervoltage warning.

VIN ON Level

(VIN tab only)

Specify the percentage of the VIN Typical Voltage, Monitored at which to consider the monitored input rail as good and start the power up sequencing of the output rails.

VOUT Power Good Assertion Level

(VOUTN tabs only)

Specify the percentage of the VOUTN Typical Voltage, Monitored at which to consider the output voltage of the rail as good and start the power up sequencing of the next output rail.

Specify the percentage of the VIN/VOUTN Typical Voltage, Monitored at which to declare an undervoltage fault.

VIN OFF Level

(VIN tab only)

Specify the percentage of the VIN Typical Voltage, Monitored at which to consider the monitored input rail as bad and start the power down sequencing of all rails.

VOUTN Power Good Deassertion Level

(VOUTN tabs only)

Specify the percentage of the VOUTN Typical Voltage, Monitored at which to consider the output voltage of the rail as bad and start the power down sequencing of all rails.

Turn this on to sequence power down for all rails, based on the fault response, if the component detects an overvoltage fault in the VIN or VOUTN rail.

Turn this on to sequence power down for all rails, based on the fault response, if the component detects an undervoltage fault in the VIN or VOUTN rail.