Floating-Point IP Cores User Guide

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ID 683750
Date 9/13/2021
Public
Document Table of Contents

1.6.1.3. Single-Extended Precision Format

The single-extended precision format contains the following binary patterns:
  • The MSB holds the sign bit.
  • The exponent and mantissa fields do not have fixed widths.
  • The minimum exponent field width is 11 bits and must be less than the width of the mantissa field.
  • The width of the mantissa field must be a minimum of 31 bits.

The sum of the widths of the sign bit, exponent field, and mantissa field must be a minimum of 43 bits and a maximum of 64 bits. The bias for the single-extended precision format is unspecified in the IEEE-754 standard. In these IP cores, a bias of 2 (WIDTH_EXP–1)1 is assumed for the single-extended precision format.

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